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Author SHA1 Message Date
David Harris
54d6a1afa2 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
David Harris
746891eac5
Merge pull request #369 from ross144/main 
Fixed issue #368 lint, but not simulation
 2023-07-26 13:32:02 -07:00
Ross Thompson
52dc71507f Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
David Harris
6e0d5d9962
Merge pull request #367 from ross144/main 
Complete removal of old flash card hardware and updates to Arty A7 to push clock speed to 20Mhz and increase memory to 256 MiB
 2023-07-25 15:26:08 -07:00
Ross Thompson
1b8edacd8d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
Ross Thompson
8dc7870e62 Updated Arty A7 fpga config and device tree to 256MiB main memory. 2023-07-25 15:11:47 -05:00
Ross Thompson
97540791de
Merge pull request #366 from davidharrishmc/dev 
Progress toward DC synthesis
 2023-07-25 11:39:49 -04:00
David Harris
0cfb5c7b3a Formatting cleanup 2023-07-25 05:11:38 -07:00
David Harris
f2623a7229 Progress toward synthesis with parameterized design 2023-07-25 05:10:53 -07:00
Ross Thompson
a543aa2b71 Removed old sdc from all configs. 2023-07-24 15:55:22 -05:00
Ross Thompson
717833b11a Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
David Harris
89332c35f2 Fixed synthesis Makefile to match new configuration 2023-07-24 11:32:46 -07:00
Ross Thompson
d418e4fa5e Updated arty a7 device clock speed for 20Mhz. 2023-07-24 11:50:00 -05:00
Ross Thompson
fd187e9ee6 Merge branch 'main' of github.com:ross144/cvw 2023-07-24 10:47:05 -05:00
Ross Thompson
d239b0649e Improved timing constraints for arty a7 to push clock speed to 20Mhz. 2023-07-24 10:46:49 -05:00
David Harris
1f54c82cdd
Merge pull request #364 from ross144/main 
Updated to the newest vivado and required removing the paramized enum. Also includes Jacob's SD card updates and new boot process.
 2023-07-22 18:52:24 -07:00
Ross Thompson
6099b0e763 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
608400ac6a Updated arty a7 device tree. 2023-07-21 19:08:45 -05:00
Ross Thompson
6e17cfba03 At least it simulates and gets through fpga elaboration. 2023-07-21 18:40:26 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
0063665baf Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
a3efddd60b
Merge pull request #365 from JacobPease/boot 
Boot
Jacob's account is passing the ECA, but there are some old commits from Jan on James Stine's account which are already in the repo which were merged into this pull request which appear as anonymous users. I don't think it's possible to fix this without a significant headache.  We'd have to cherry-pick each of Jacob's 21 commits.  I'm planning to merge his work into main today/weekend and this will make the job harder. Since these commits are already part of main I'm going to merge this.
 2023-07-21 17:26:41 -04:00
Ross Thompson
37078f3d9b Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
7873d26678 Fixed a bunch of timing constraints for the arty a7 board. 2023-07-19 17:08:16 -05:00
Ross Thompson
9ba3113e9c Improved critical path. 2023-07-19 14:59:37 -05:00
Ross Thompson
936b2a8c8b Optimized critial path in ifu's spill logic. 2023-07-19 14:13:46 -05:00
Ross Thompson
bae5359c6b Fixed typo in fpga top for arty a7. 2023-07-19 11:37:29 -05:00
Ross Thompson
2854452ecc Removed all old configuration files. 2023-07-19 10:28:54 -05:00
Ross Thompson
0e22fe5231 Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
Ross Thompson
60609857a9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-18 17:16:33 -05:00
Ross Thompson
3bf2b35704 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
930e00b69b Added new submodule for digilent fpga boards. 2023-07-17 16:25:37 -05:00
Ross Thompson
cc8826a15a Merge branch 'main' of github.com:ross144/cvw 2023-07-17 16:01:05 -05:00
Ross Thompson
a5f75d568b Added artya7 device tree. 2023-07-17 16:01:02 -05:00
Ross Thompson
5ce4ac963f Updated arty a7 fpga top. 2023-07-17 15:55:57 -05:00
Ross Thompson
c7283f8c83 Merge branch 'main' of github.com:ross144/cvw 2023-07-17 15:52:27 -05:00
Ross Thompson
80093a0eb1 Updated the FPGA zero stage bootloader. 2023-07-17 15:52:13 -05:00
David Harris
8c807ce3ef
Merge pull request #363 from ross144/main 
Fixed over logging issue with icache and dcache loggers.
 2023-07-15 06:19:11 -07:00
Ross Thompson
20751790f6 Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations. 2023-07-14 16:31:44 -05:00
Ross Thompson
6ddd8d4e2b Fixed the icache and dcache overlogging issue. 2023-07-14 15:47:05 -05:00
Jacob Pease
142ec857ed Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
Ross Thompson
b4d9d2370c Somehow the Arty A7 device tree was missing. 2023-07-13 14:10:45 -05:00
Ross Thompson
de5cab2bc6 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-13 11:26:49 -05:00
Ross Thompson
cebcf1995c
Merge pull request #361 from davidharrishmc/dev 
Clean up privilege rs1 decoding and implement svinval as sfence.vma
 2023-07-13 12:26:30 -04:00
David Harris
45667c9f4d Clean up privilege rs1 decoding and implement svinval as sfence.vma 2023-07-13 02:41:17 -07:00
David Harris
40ac1f7872
Merge pull request #360 from ross144/main 
Fixed the privilege decoder bug which prevented the fpga linux boot.
 2023-07-13 01:40:28 -07:00
Ross Thompson
96b8f34d1a Got xcelium running wally, but it fails to actually preload the memories. 2023-07-12 13:56:57 -05:00
Ross Thompson
add1a6996e Merge branch 'main' of github.com:ross144/cvw 2023-07-11 15:09:07 -05:00
Ross Thompson
f30c92e82a Added wfi and interrupt to tracer. 2023-07-11 15:09:04 -05:00