David Harris
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0421b7af56
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Changes for floating point sims
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2021-10-27 10:37:35 -07:00 |
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David Harris
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f793dd7a5e
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removed unused signal from wave.do
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2021-10-26 09:02:22 -07:00 |
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bbracker
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f39a509b5b
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adapt testbench linux to use reset_ext
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2021-10-25 13:26:44 -07:00 |
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bbracker
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2c9c9328a9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-25 12:25:37 -07:00 |
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bbracker
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c61cbf9618
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change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
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2021-10-25 12:25:32 -07:00 |
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David Harris
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47124f36c8
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Added synchronizer to reset
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2021-10-25 10:05:41 -07:00 |
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bbracker
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9423b90780
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switch linux graphical sim over to Ross's waves
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2021-10-24 18:39:23 -07:00 |
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bbracker
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4544d28bc9
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or actually needed to reduce expectations of buildroot
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2021-10-24 06:59:34 -07:00 |
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bbracker
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23bff55c6e
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increase regression's expectations of buildroot
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2021-10-24 06:50:22 -07:00 |
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bbracker
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366cb12a13
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buildroot do scripts now compile flops
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2021-10-23 23:14:59 -07:00 |
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bbracker
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3b63dde570
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-23 13:17:37 -07:00 |
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bbracker
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d6fb441666
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add option for regression to do a partial execution of buildroot
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2021-10-23 13:17:30 -07:00 |
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David Harris
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67f3fc9962
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wrapping up lint cleanup; many unused signals removed
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2021-10-23 12:15:14 -07:00 |
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David Harris
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bf3eb7b814
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update scripts for handling src/*/* subdirectories
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2021-10-23 08:54:29 -07:00 |
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David Harris
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8b854bb1c2
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Cleaned up LINT erors
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2021-10-23 06:28:49 -07:00 |
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David Harris
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3407b63c8a
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Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
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2021-10-23 06:15:26 -07:00 |
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James E. Stine
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eb64a7f0c9
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Update to fpdivsqrt to go on posedge as it should. Also an update to
individual regression test for TestFloat (still needs some tweaking)
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2021-10-13 17:14:42 -05:00 |
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bbracker
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886a650da4
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change infrastructure to expect only 6.3 million from buildroot
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2021-10-12 10:41:15 -07:00 |
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David Harris
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a8ce4568aa
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Divider FSM simplification
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2021-10-10 22:24:14 -07:00 |
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David Harris
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a077735ecc
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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bbracker
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50e5b0a8f4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-10 13:12:44 -07:00 |
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bbracker
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efe9f5d857
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make regression expect what buildroot is actually able to reach
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2021-10-10 13:12:36 -07:00 |
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David Harris
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bfe8bf3855
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Removed negedge flops from divider
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2021-10-10 10:41:13 -07:00 |
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bbracker
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64a3043a88
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update wave-do
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2021-10-07 19:16:52 -04:00 |
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James E. Stine
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739e17ddac
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Add generic wave command file
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2021-10-06 13:17:49 -05:00 |
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James E. Stine
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658dcc8c1b
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Update to testbench for FP stuff
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2021-10-06 13:16:38 -05:00 |
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David Harris
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9809e57d0c
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Replacing XE and DE with SrcAE and SrcBE in divider
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2021-10-03 11:11:53 -04:00 |
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David Harris
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8f36297569
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Added suffixes to more divider signals
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2021-10-03 00:32:58 -04:00 |
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David Harris
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24bb3f4baf
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Added more pipeline stage suffixes to divider
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2021-10-02 22:54:01 -04:00 |
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David Harris
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fe69513bb7
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Partial divider cleanup
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2021-10-02 20:55:37 -04:00 |
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David Harris
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d4437b842a
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Divider code cleanup
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2021-10-02 10:13:49 -04:00 |
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David Harris
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0e0e204d3d
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Moved negating divider otuput to M stage
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2021-10-02 10:03:02 -04:00 |
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David Harris
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e1ad732178
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SRT Division unsigned passing Imperas tests
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2021-09-30 12:17:24 -04:00 |
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Ross Thompson
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d09b381183
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Fixed the amo on dcache miss cpu stall issue.
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2021-09-17 22:15:03 -05:00 |
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Ross Thompson
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99d675b872
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Finished adding the d cache flush. Required ensuring the write data, address, and size are
correct when transmitting to AHBLite interface.
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2021-09-17 13:03:04 -05:00 |
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Ross Thompson
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b92070a67a
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Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
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2021-09-17 10:25:21 -05:00 |
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Ross Thompson
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d4398c23fb
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Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
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2021-09-16 18:32:29 -05:00 |
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Ross Thompson
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eb7b5f1d63
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Added invalidate to icache.
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2021-09-16 16:15:54 -05:00 |
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bbracker
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92ddc9b20a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-09-15 17:31:11 -04:00 |
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bbracker
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b1be8f4858
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fix regression
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2021-09-15 17:30:59 -04:00 |
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David Harris
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72c1cc33f5
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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David Harris
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654f3d1940
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Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
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2021-09-13 12:40:40 -04:00 |
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David Harris
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1847198da9
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Cleaned up wally-arch test scripts
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2021-09-13 00:02:32 -04:00 |
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David Harris
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cb624fe679
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Lint cleaning, riscv-arch-test testing
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2021-09-09 11:05:12 -04:00 |
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David Harris
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a31828e925
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-09-08 16:00:12 -04:00 |
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David Harris
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30e2ec3987
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Added testbench-arch for riscv-arch-test suite
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2021-09-08 15:59:40 -04:00 |
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Ross Thompson
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6606eea27e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-09-08 12:47:03 -05:00 |
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Ross Thompson
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5bc90ef32f
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Slight modification to wave file.
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2021-09-08 10:40:46 -05:00 |
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bbracker
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5e9a39e755
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fixed bug where M mode was sensitive to S mode traps
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2021-09-07 19:14:39 -04:00 |
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bbracker
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28fed18421
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No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
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2021-09-06 22:59:54 -04:00 |
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