Jordan Carlin
|
518650a756
|
Attempt to fix buildroot makefile
|
2024-07-25 22:26:34 -07:00 |
|
Jordan Carlin
|
fed45d9eb6
|
Move verilator stack limit to setup.sh/csh insteaed of site-setup
|
2024-07-25 21:35:52 -07:00 |
|
Jordan Carlin
|
e851812608
|
Replace /opt/riscv after merge
|
2024-07-25 21:33:31 -07:00 |
|
Jordan Carlin
|
42a9bbf28d
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
|
2024-07-25 21:21:57 -07:00 |
|
Jordan Carlin
|
22d2077006
|
Cleanup
|
2024-07-25 21:16:00 -07:00 |
|
Rose Thompson
|
6f78a60468
|
Merge pull request #896 from davidharrishmc/dev
Updated ImperasTG derived config to turn off peripherals
|
2024-07-25 12:20:31 -05:00 |
|
David Harris
|
da853b45e6
|
Updated ImperasTG derived config to turn off peripherals
|
2024-07-25 10:08:34 -07:00 |
|
Rose Thompson
|
6496454054
|
Merge pull request #895 from davidharrishmc/dev
Fix Issue 894 about floating-point decoding of reserved rm/frm
|
2024-07-25 11:51:32 -05:00 |
|
David Harris
|
faa1378920
|
Legalized PMPconfig WARL
|
2024-07-25 09:43:54 -07:00 |
|
David Harris
|
d5af25ffbf
|
CHeck legal rnum field when decoding aes64ks1i
|
2024-07-25 09:19:23 -07:00 |
|
David Harris
|
5bf7250687
|
Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt
|
2024-07-25 09:09:13 -07:00 |
|
David Harris
|
f7dd49cc6c
|
Issue #894: trap on floating-point ops with reserved rounding modes
|
2024-07-25 06:59:58 -07:00 |
|
Jordan Carlin
|
4b86f85904
|
Linux readme updates
|
2024-07-24 20:19:30 -07:00 |
|
Jordan Carlin
|
a9cd457536
|
Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed)
|
2024-07-24 20:19:30 -07:00 |
|
Jordan Carlin
|
676c6b88a0
|
Automatically determine number of threads to use in wally-tool-chain-install
|
2024-07-24 20:19:30 -07:00 |
|
Jordan Carlin
|
e6b3257862
|
Build nproc linux
|
2024-07-24 20:19:30 -07:00 |
|
Jordan Carlin
|
85b98af958
|
Build testvectors with buildroot
|
2024-07-24 20:19:30 -07:00 |
|
Jordan Carlin
|
bbf90b1f4b
|
Add cpio to installation for buildroot
|
2024-07-24 19:55:18 -07:00 |
|
David Harris
|
2c7bc7038e
|
Merge pull request #892 from ross144/main
Adds synthesizable RVVI FPGA hardware
|
2024-07-24 12:21:36 -07:00 |
|
Rose Thompson
|
ce61429bdf
|
Fixed the reset bug in wallyTracer.
|
2024-07-24 13:32:46 -05:00 |
|
Rose Thompson
|
5cae55561e
|
Removed unused file.
|
2024-07-24 13:30:25 -05:00 |
|
Rose Thompson
|
df88939bcb
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-07-24 13:14:25 -05:00 |
|
Rose Thompson
|
d0a5b278b7
|
Factored out the rvvi testbench code into rvvitbwrapper.
|
2024-07-24 13:10:57 -05:00 |
|
Rose Thompson
|
b1a711ae0f
|
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
|
2024-07-24 12:47:50 -05:00 |
|
Rose Thompson
|
27f89fcdbd
|
Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
|
2024-07-24 10:13:03 -05:00 |
|
Jordan Carlin
|
bb5c9f9ead
|
Switch to logger function and fix exit codes
|
2024-07-23 23:42:03 -07:00 |
|
Jordan Carlin
|
d08deddcc4
|
Update logging grep
|
2024-07-23 23:40:42 -07:00 |
|
Jordan Carlin
|
121ee51503
|
Fix logging
|
2024-07-23 23:40:03 -07:00 |
|
Jordan Carlin
|
47452ddaaa
|
Remove hardcoded /opt/riscv
|
2024-07-23 23:29:45 -07:00 |
|
Rose Thompson
|
9404a339ee
|
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
|
2024-07-23 17:44:37 -05:00 |
|
Rose Thompson
|
6c212ebf0e
|
Changes are confirmed to work on the FPGA.
|
2024-07-23 17:39:38 -05:00 |
|
Rose Thompson
|
e8e71ad643
|
Code cleanup.
|
2024-07-23 16:35:05 -05:00 |
|
Rose Thompson
|
57ea39d685
|
Fixed rvvi csr counting.
|
2024-07-23 16:22:23 -05:00 |
|
Rose Thompson
|
54e0289608
|
Fixed bugs in the rvvi synth logic which encoded csr instructions.
|
2024-07-23 16:16:11 -05:00 |
|
Rose Thompson
|
1eff86b7ae
|
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
|
2024-07-23 13:18:03 -05:00 |
|
Rose Thompson
|
c463201d68
|
Moved all rvvi files to rvvi directory.
|
2024-07-23 13:03:21 -05:00 |
|
Rose Thompson
|
825dbefcb2
|
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
|
2024-07-23 12:26:03 -05:00 |
|
Rose Thompson
|
bb74a0f96b
|
Resolved more lint errors in the rvvi synthesized hardware.
|
2024-07-23 12:23:04 -05:00 |
|
Rose Thompson
|
42f2469ea7
|
Merge pull request #891 from davidharrishmc/dev
Increased covergen.py functional coverage to 87.6%
|
2024-07-23 09:34:13 -05:00 |
|
David Harris
|
a4a0a10879
|
Increased covergen.py functional coverage to 87.6%
|
2024-07-23 04:38:13 -07:00 |
|
Jordan Carlin
|
36ffeb2dca
|
Fix minimum scipy version for Ubuntu20.04
|
2024-07-23 01:03:10 -07:00 |
|
Jordan Carlin
|
d096e2e4f8
|
Fix python version for Ubuntu 20.04
|
2024-07-23 00:16:27 -07:00 |
|
Jordan Carlin
|
e4c38dd766
|
Add logs and reduce console output
|
2024-07-22 23:13:38 -07:00 |
|
Jordan Carlin
|
d045fb6662
|
Update python versions
|
2024-07-22 23:12:48 -07:00 |
|
Jordan Carlin
|
16dd728ed6
|
Use requirements file for pip packages
|
2024-07-22 23:12:27 -07:00 |
|
Jordan Carlin
|
4e8cc68d3e
|
Add DEBIAN_FRONTEND=noninteractive to apt
|
2024-07-22 23:11:33 -07:00 |
|
Jordan Carlin
|
8c8e1a3fef
|
Update section header function usage
|
2024-07-22 23:10:45 -07:00 |
|
Rose Thompson
|
94a1ce32e7
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-07-22 17:48:34 -05:00 |
|
Rose Thompson
|
8ca565ed53
|
Updated for a better ILA rvvi debugger.
|
2024-07-22 17:44:04 -05:00 |
|
Rose Thompson
|
121342f4cc
|
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
|
2024-07-22 16:12:06 -05:00 |
|