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517cae796c
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Author SHA1 Message Date
Ross Thompson
517cae796c Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
e438592476 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-03 17:56:00 -06:00
Ross Thompson
41258529f0 Fixed bug in the top level of fpga verilog. 2021-12-03 17:55:36 -06:00
Ross Thompson
cb744280c3 Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Skylar Litz
a69ab3bd1b fix some interrupt timing bugs 2021-12-03 12:32:38 -08:00
Ross Thompson
35dd1b5c9f Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 10:05:13 -06:00
Ross Thompson
755c3e6a4c Fixed buildroot to work with the fpga's merge. 2021-12-02 18:09:43 -06:00
Ross Thompson
74ffb48c0a Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
b7e8c74e61 Merge branch 'fpga' into main 2021-12-02 14:28:10 -06:00
Ross Thompson
5d4051d1c2 Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
kwan
e4f214090d .* resolved in ifu.sv 2021-12-02 10:32:35 -08:00
kwan
2a77bc8053 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
Ross Thompson
2cfbdb1c47 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
2a7467c76d Separated timing constraints from ILA. 2021-12-01 18:15:04 -06:00
Ross Thompson
6a228ade04 Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
David Harris
2519d7705b Merged makefile changes 2021-12-01 10:39:26 -08:00
David Harris
6d936ee499 Makefile organization 2021-12-01 10:38:46 -08:00
Kevin Kim
c2274ce18e Makefile cleaning 2021-12-01 10:06:54 -08:00
David Harris
e4861e11d1 Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
David Harris
40acc70e21 Updated Makefile 2021-12-01 09:06:33 -08:00
Kevin Kim
fcbbb3d198 Makefile up and running 2021-11-30 23:02:02 -08:00
Kevin Kim
fa73180ce4 changed readme to reflect submodule updates 2021-11-30 18:26:49 -08:00
Kevin Kim
869cd44533 added arch-test submodule 2021-11-30 18:22:08 -08:00
Kevin Kim
6323609da9 Added git submodules 
-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
 2021-11-30 18:16:37 -08:00
Ross Thompson
96926877c4 Created top level FPGA module which replicates the schematic of the initial fpga design. 2021-11-30 17:18:28 -06:00
David Harris
273e211660 testing push 2021-11-30 11:20:09 -08:00
David Harris
2060140337 Coremark updates 2021-11-30 11:16:13 -08:00
Ross Thompson
7f52d86980 Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
84116a756e Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
d7df9c1054 Fixed uart for FPGA config after merge. This still needs some work. 2021-11-29 16:07:54 -06:00
Ross Thompson
ce91732856 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00
David Harris
998ebac825 coremark makefile 2021-11-29 13:33:01 -08:00
Ross Thompson
9a0bf54840 Created tcl scripts to build 2 of the 4 xilinx IP. 2021-11-29 11:26:08 -06:00
Ross Thompson
8e4eacc18e Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
c5d393fbc6 UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses 2021-11-25 11:01:59 -08:00
Noah Limpert
cb77c1db3a updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well 2021-11-24 23:22:04 -08:00
Noah Limpert
e66fdd3f80 replaced .* instation of priv module on wallypiplinedhart 2021-11-24 22:58:59 -08:00
Noah Limpert
0cd31bfc1f Made abhlite instation on wallypipehart more clear, updated spacing for consistency 2021-11-24 22:48:01 -08:00
Noah Limpert
8a64510ee4 updated module instation of LSU on wallypiplinedhard 2021-11-24 22:09:39 -08:00
bbracker
de8e2008d2 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
Ross Thompson
b909375289 Missed another change to uart. 2021-11-23 10:20:47 -06:00
Ross Thompson
fe00729d7c Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation. 2021-11-23 10:00:32 -06:00
Ross Thompson
e309017ec4 Added QEMU hack for initial LCR value in uart. 2021-11-22 15:23:19 -06:00
Ross Thompson
e568068c78 Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed. 2021-11-22 15:20:54 -06:00
Ross Thompson
fcd14828d4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-22 11:30:14 -06:00
bbracker
d90d708cf9 activate STVAL for buildroot 2021-11-21 10:40:28 -08:00
Ross Thompson
c661bb4894 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-20 22:44:45 -06:00
Ross Thompson
d080041508 Removed unneeded check for icache ways. 2021-11-20 22:44:37 -06:00