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Author SHA1 Message Date
bbracker
8f73c1df9e 2nd attempt at making regression-wally.py able to be run from a different dir 2021-12-07 13:13:30 -08:00
bbracker
979580b1e7 fix checkpointing so that it can find the synchronized reset signal 2021-12-07 13:12:06 -08:00
bbracker
302bc56646 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-07 11:16:51 -08:00
bbracker
010339fa05 attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly 2021-12-07 11:16:43 -08:00
Ross Thompson
4dbd5d45ee Added information on how to copy the linux image to flash card. 2021-12-07 13:16:38 -06:00
bbracker
2229e66d6c add buildroot tv linking to make-tests.sh 2021-12-07 11:15:59 -08:00
Ross Thompson
6c6b7865fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-07 13:12:59 -06:00
Ross Thompson
22721dd923 Added generate around the dtim preload. 
Added readme to explain FPGA.
 2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
bbracker
5a73ecd0be regression.py bugfix 2021-12-06 19:32:38 -08:00
bbracker
4df9093a7f add make-tests scripts 2021-12-06 15:37:33 -08:00
bbracker
7c44ecb364 add buildroot-only option to regression 2021-12-06 14:13:58 -08:00
bbracker
524bb0aa9a linux-testvectors symlinks shouldn't be in repo, especially not in this location 2021-12-05 22:03:51 -08:00
Ross Thompson
c3c9c327b7 Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Kip Macsai-Goren
7f5b993ea5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-05 20:04:46 +00:00
David Harris
f45fe48158 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-04 20:26:01 -08:00
David Harris
64f33161bc Added files to repo 2021-12-04 20:25:33 -08:00
Ross Thompson
3f692ac89a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-03 17:56:00 -06:00
Ross Thompson
955ddcfbe1 Fixed bug in the top level of fpga verilog. 2021-12-03 17:55:36 -06:00
Ross Thompson
5b4ff4526e Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Skylar Litz
546f7fb4c2 fix some interrupt timing bugs 2021-12-03 12:32:38 -08:00
Kip Macsai-Goren
8efce35f87 Edited the chenge privilege mode tests for clarity of use 2021-12-03 10:07:37 -08:00
Kip Macsai-Goren
df918d8ca0 added corrected exectue tests to pmp tests 2021-12-03 10:00:57 -08:00
Ross Thompson
cbb5e4440f Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 10:05:13 -06:00
Ross Thompson
500e6ff430 Fixed buildroot to work with the fpga's merge. 2021-12-02 18:09:43 -06:00
Ross Thompson
b03ca464f1 Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
9ccc8e7f3a Merge branch 'fpga' into main 2021-12-02 14:28:10 -06:00
Ross Thompson
96fb3acefd Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
kwan
5164129172 .* resolved in ifu.sv 2021-12-02 10:32:35 -08:00
kwan
05a838aee2 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
Ross Thompson
303324d370 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
0d47749cb5 Separated timing constraints from ILA. 2021-12-01 18:15:04 -06:00
Ross Thompson
e94fb2aaec Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
David Harris
3b0989125f Merged makefile changes 2021-12-01 10:39:26 -08:00
David Harris
ca1d0cf12e Makefile organization 2021-12-01 10:38:46 -08:00
Kevin Kim
67eabfdacc Makefile cleaning 2021-12-01 10:06:54 -08:00
David Harris
42780ba40b Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
David Harris
6874697451 Updated Makefile 2021-12-01 09:06:33 -08:00
Kevin Kim
ea979c7277 Makefile up and running 2021-11-30 23:02:02 -08:00
Kevin Kim
9a5b9922fa changed readme to reflect submodule updates 2021-11-30 18:26:49 -08:00
Kevin Kim
cae3a44b9a added arch-test submodule 2021-11-30 18:22:08 -08:00
Kevin Kim
b5e86b2e20 Added git submodules 
-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
 2021-11-30 18:16:37 -08:00
Ross Thompson
5ea9ec0ae6 Created top level FPGA module which replicates the schematic of the initial fpga design. 2021-11-30 17:18:28 -06:00
David Harris
a146d7a618 testing push 2021-11-30 11:20:09 -08:00
David Harris
ce50b1010d Coremark updates 2021-11-30 11:16:13 -08:00
Ross Thompson
d5f445e0fd Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
a528a86607 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
51807379a8 Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
97c73f10ff Fixed uart for FPGA config after merge. This still needs some work. 2021-11-29 16:07:54 -06:00
Ross Thompson
8aa87958a9 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00