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Fixed more constraint issues in fpga.

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Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
This commit is contained in:
Ross Thompson 2021-12-05 15:14:18 -06:00
parent 3f692ac89a
commit c3c9c327b7
4 changed files with 86 additions and 95 deletions
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2
fpga/constraints/constraints.xdc
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@ -282,7 +282,7 @@ set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
set_max_delay -datapath_only -from [get_pins wrapper_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins wrapper_i/proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]

175
fpga/constraints/debug.xdc
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File diff suppressed because one or more lines are too long

2
fpga/generator/wally.tcl
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@ -130,6 +130,8 @@ report_utilization -hierarchical -file re
report_cdc -file reports/cdc.rpt
report_clock_interaction -file reports/clock_interaction.rpt
source ../constraints/debug2.xdc
# set for RuntimeOptimized implementation
#set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]

2
wally-pipelined/src/uncore/dtim.sv
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@ -51,7 +51,6 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
initial begin
//$readmemh(PRELOAD, RAM);
/* -----\/----- EXCLUDED -----\/-----
// FPGA only
RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081;
@ -95,7 +94,6 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
RAM[39] = 64'h1047278367498082;
RAM[40] = 64'h67c98082dfed8b85;
RAM[41] = 64'h0000808210a7a023;
-----/\----- EXCLUDED -----/\----- */
end
assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);