11 Commits

Author	SHA1	Message	Date
Rose Thompson	38ddbf860e	Fixed bug with mmcm not generating the 4th clock.	2024-05-30 16:19:28 -05:00
Rose Thompson	9703055758	The FPGA is synthesizing with the rvvi and ethernet hardware.	2024-05-30 15:37:17 -05:00
Rose Thompson	6b7ff50a84	Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.	2023-11-13 16:44:02 -06:00
Ross Thompson	06efd2cdde	Pushed performance of arty a7 to 23Mhz.	2023-07-31 14:13:09 -05:00
Ross Thompson	065e5e98c9	Improved timing constraints for arty a7 to push clock speed to 20Mhz.	2023-07-24 10:46:49 -05:00
Ross Thompson	2752e5de4c	Fixed a bunch of timing constraints for the arty a7 board.	2023-07-19 17:08:16 -05:00
Ross Thompson	30d017c258	Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.	2023-04-17 12:16:31 -05:00
Ross Thompson	fe692dacce	Finally got the arty a7 to build.	2023-04-17 11:54:22 -05:00
Ross Thompson	4ad33d7acc	OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(	2023-04-17 11:10:19 -05:00
Ross Thompson	5591b447d6	Fixed more issues with arty a7 constarints.	2023-04-16 13:25:02 -05:00
Ross Thompson	2f8359e6cc	Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.	2023-04-14 18:02:16 -05:00