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Author	SHA1	Message	Date
Kip Macsai-Goren	87ba45ce36	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 21:30:51 +00:00
Kip Macsai-Goren	0ee4e03cd6	fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh.	2022-01-04 21:30:38 +00:00
David Harris	57daff45c8	Fixed bad address for F/fmsub_b18-01	2022-01-04 21:04:06 +00:00
Kip Macsai-Goren	ad3ee6bc08	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 20:58:08 +00:00
David Harris	1f07470477	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 19:47:51 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
Kip Macsai-Goren	d1709e98d2	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 18:16:46 +00:00
Ross Thompson	f3a300738f	Added mmu tests to regression-wally. ... imperas64mmu passes but imperas32mmu does not.	2022-01-04 11:13:36 -06:00
Ross Thompson	7ac412eb8e	Modified dcache to ensure nontranslated index is used.	2022-01-04 10:53:53 -06:00
Kip Macsai-Goren	9ad44e3e97	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 06:38:28 +00:00
Ross Thompson	1ea267cab5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-03 23:49:28 -06:00
Ross Thompson	08b439b9e9	Fixed icache stalling cpu when doing an uncached operation.	2022-01-03 23:49:19 -06:00
Kip Macsai-Goren	cc0409b9d6	update 64 bit tests to make make work correctly and general cleanup	2022-01-04 05:02:33 +00:00
Kip Macsai-Goren	cbe255230e	Update 32 bit memory tests to make make work correcttly and generally cleanup	2022-01-04 04:59:47 +00:00
Kip Macsai-Goren	a74b0b8f56	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 04:55:36 +00:00
Ross Thompson	4b4aa11684	Reordered inputs/outputs in caches.	2022-01-03 22:52:50 -06:00
Ross Thompson	fa39de9cef	Added generate around the spill logic so it is only used if supporting compressed instructions.	2022-01-03 22:23:04 -06:00
Ross Thompson	36451bbd15	Minor improvement to icache.	2022-01-03 22:00:35 -06:00
Ross Thompson	a130c03478	More Icache clean up.	2022-01-03 21:22:34 -06:00
Ross Thompson	c2a9b3bc79	Major icache cleanup.	2022-01-03 21:12:17 -06:00
Ross Thompson	5a438a9498	Removed spill support from icache.	2022-01-03 21:03:02 -06:00
Ross Thompson	697717707f	The ifu now directly supports compressed without the icache providing the implemenation. ... The icache still constains all the orignal muxing logic to handle spills. This should be removed.	2022-01-03 20:49:47 -06:00
Ross Thompson	b7b9e3bd55	Almost working compressed instructions with compressed detection and processing in ifu rather than icache.	2022-01-03 18:10:15 -06:00
Ross Thompson	3adc0d43e7	Prepared the ifu and icache for moving spills to ifu.	2022-01-03 17:09:36 -06:00
Ross Thompson	35c5b9ad50	Fixed bug with the icache.	2022-01-03 15:55:19 -06:00
Ross Thompson	e0c310fea7	Fixed a bug where the instruction fetch got out of sync with the icache.	2022-01-03 13:27:15 -06:00
David Harris	d909e8f371	Replaced && and || with & and | in non-fp files per new style guidelines	2022-01-02 21:47:21 +00:00
David Harris	9693110857	Started adding asynchronous TIMECLK for CLINT	2022-01-02 21:18:16 +00:00
Katherine Parry	9d4e1671c9	some errors in FP ArchTests fixed	2022-01-01 23:50:23 +00:00
David Harris	8d6c48cfb1	Removed .* from MMU.	2021-12-31 07:19:51 +00:00
David Harris	41052178ce	Removed .* from CSRs	2021-12-31 07:11:03 +00:00
David Harris	470bb6ed4d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-31 06:40:25 +00:00
David Harris	9f24b4c969	Simplified performance counters	2021-12-31 06:40:21 +00:00
Ross Thompson	b146c71b14	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-30 18:10:36 -06:00
Ross Thompson	b6fbc4a1e3	Added mux to select between uncache instruction requests and cached instructions requests. ... Cacheless design almost works with the exception of compressed instructions.	2021-12-30 18:09:37 -06:00
Ross Thompson	58ef91c94b	Fixed wave.do.	2021-12-30 17:57:07 -06:00
Ross Thompson	5904bc68c7	Patched up the linux-wave.do file.	2021-12-30 17:53:43 -06:00
David Harris	42df98bc6d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-30 23:40:02 +00:00
David Harris	b96439dd73	Fixes to counters; buildroot still broken	2021-12-30 23:39:59 +00:00
Ross Thompson	8e4467654a	Working without dcache.	2021-12-30 16:01:31 -06:00
Ross Thompson	91f67f19a7	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-30 15:52:15 -06:00
Ross Thompson	6c45da022b	Progress on non dcache mode working.	2021-12-30 15:51:07 -06:00
David Harris	4f052b1ab5	Moved SDC folder into uncore	2021-12-30 21:38:24 +00:00
Ross Thompson	9136b1fd73	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-30 15:26:41 -06:00
Ross Thompson	6b59c03d1b	No dcache now supported. Does not pass regression tests however.	2021-12-30 15:26:32 -06:00
David Harris	347896064d	Removed unnecessary generate inside hptw	2021-12-30 21:21:00 +00:00
David Harris	8225f85b86	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-30 21:15:00 +00:00
David Harris	7847ff33fc	Removed carry-save multiplier option from muldiv	2021-12-30 21:14:57 +00:00
Ross Thompson	c79e14fec5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-30 14:56:24 -06:00
Ross Thompson	b6c9d01f8b	Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.	2021-12-30 14:56:17 -06:00