Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/src/cache/dcache.sv

@@ -30,34 +30,35 @@ module dcache
    input logic 								reset,
    input logic 								CPUBusy,
 
+   // mmu
+   input logic 								CacheableM,
    // cpu side
    input logic [1:0] 						LsuRWM,
    input logic [1:0] 						LsuAtomicM,
    input logic 								FlushDCacheM,
    input logic [11:0] 						LsuAdrE, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0] 				LsuPAdrM, // physical address
-  
    input logic [`XLEN-1:0] 					FinalWriteDataM,
    output logic [`XLEN-1:0] 				ReadDataWordM,
-   output logic 							DCacheStall,
-   output logic 							DCacheMiss,
-   output logic 							DCacheAccess,
-   output logic 							DCacheCommittedM,
-   output logic 							DCacheWriteLine,
-   output logic 							DCacheFetchLine,
-   input logic 								DCacheBusAck,
-  
+   output logic 							DCacheCommittedM,   
 
+   // Bus fsm interface
+   input logic 								IgnoreRequest,
+   output logic 							DCacheFetchLine,
+   output logic 							DCacheWriteLine,
+
+   input logic 								DCacheBusAck,
    output logic [`PA_BITS-1:0] 				DCacheBusAdr,
-   output logic [`XLEN-1:0] 				ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0],
+
 
    input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData,
+   output logic [`XLEN-1:0] 				ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0],
 
+   output logic 							DCacheStall,
 
-   // inputs from TLB and PMA/P
-   input logic 								CacheableM,
-   // from ptw
-   input logic 								IgnoreRequest
+   // to performance counters
+   output logic 							DCacheMiss,
+   output logic 							DCacheAccess
    );
 
   localparam integer 						BLOCKLEN = `DCACHE_BLOCKLENINBITS;

wally-pipelined/src/cache/icache.sv

@@ -29,26 +29,26 @@ module icache
   (
    // Basic pipeline stuff
    input logic 								clk, reset,
-   input logic 								CPUBusy, 
+   input logic 								CPUBusy,
+
+   // mmu
+   input logic 								CacheableF,
+
+   // cpu side 
+   input logic 								InvalidateICacheM,
    input logic [11:0] 						PCNextF,
    input logic [`PA_BITS-1:0] 				PCPF,
    input logic [`XLEN-1:0] 					PCF,
 
+   // bus fsm interface
    input logic 								IgnoreRequest,
-  
-   // Data read in from the ebu unit
    input logic [`ICACHE_BLOCKLENINBITS-1:0] ICacheMemWriteData,
    output logic 							ICacheFetchLine,
 
    (* mark_debug = "true" *) input logic 	ICacheBusAck,
-   // Read requested from the ebu unit
    (* mark_debug = "true" *) output logic [`PA_BITS-1:0] ICacheBusAdr,
-   // High if the instruction currently in the fetch stage is compressed
-   //output logic 							CompressedF,
    // High if the icache is requesting a stall
    output logic 							ICacheStallF,
-   input logic 								CacheableF,
-   input logic 								InvalidateICacheM,
   
    // The raw (not decompressed) instruction that was requested
    // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros

wally-pipelined/src/cache/icachefsm.sv

@@ -86,6 +86,7 @@ module icachefsm
 		if(IgnoreRequest) begin
 		  SelAdr = 1'b1;
 		  NextState = STATE_READY;
+		  ICacheStallF = 1'b0;
 		end
 		else if (CacheableF & hit) begin
           ICacheStallF = 1'b0;
@@ -103,7 +104,9 @@ module icachefsm
 		  if(CPUBusy) begin
 			NextState = STATE_CPU_BUSY;
 			SelAdr = 1'b1;
+			ICacheStallF = 1'b0;
 		  end else begin
+			ICacheStallF = 1'b0;
             NextState = STATE_READY;
 		  end
         end

wally-pipelined/src/ifu/ifu.sv

@@ -350,8 +350,6 @@ module ifu (
   // branch and jump predictor
   generate
     if (`BPRED_ENABLED == 1) begin : bpred
-      // I am making the port connection explicit for now as I want to see them and they will be changing.
-    
       bpred bpred(.clk, .reset,
 				  .StallF, .StallD, .StallE,
 				  .FlushF, .FlushD, .FlushE,