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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added generate around the spill logic so it is only used if supporting compressed instructions.
This commit is contained in:
Ross Thompson
parent
36451bbd15
commit
fa39de9cef
@ -27,61 +27,54 @@
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`include "wally-config.vh"
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module ifu (
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushF, FlushD, FlushE, FlushM, FlushW,
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// Fetch
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input logic [`XLEN-1:0] IfuBusHRDATA,
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input logic IfuBusAck,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
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output logic [`PA_BITS-1:0] IfuBusAdr,
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output logic IfuBusRead,
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output logic IfuStallF,
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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input logic PCSrcE,
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input logic [`XLEN-1:0] IEUAdrE,
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output logic [`XLEN-1:0] PCE,
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output logic BPPredWrongE,
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// Mem
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input logic RetM, TrapM,
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input logic [`XLEN-1:0] PrivilegedNextPCM,
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input logic InvalidateICacheM,
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output logic [31:0] InstrD, InstrM,
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output logic [`XLEN-1:0] PCM,
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output logic [4:0] InstrClassM,
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output logic BPPredDirWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic BPPredClassNonCFIWrongM,
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// Writeback
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// output logic [`XLEN-1:0] PCLinkW,
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// Faults
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input logic IllegalBaseInstrFaultD,
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output logic ITLBInstrPageFaultF,
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output logic IllegalIEUInstrFaultD,
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output logic InstrMisalignedFaultM,
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output logic [`XLEN-1:0] InstrMisalignedAdrM,
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input logic ExceptionM, PendingInterruptM,
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// mmu management
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PTE,
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input logic [1:0] PageType,
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic ITLBWriteF, ITLBFlushF,
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output logic ITLBMissF,
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushF, FlushD, FlushE, FlushM, FlushW,
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// Bus interface
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input logic [`XLEN-1:0] IfuBusHRDATA,
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input logic IfuBusAck,
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output logic [`PA_BITS-1:0] IfuBusAdr,
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output logic IfuBusRead,
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output logic IfuStallF,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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input logic PCSrcE,
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input logic [`XLEN-1:0] IEUAdrE,
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output logic [`XLEN-1:0] PCE,
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output logic BPPredWrongE,
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// Mem
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input logic RetM, TrapM,
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input logic [`XLEN-1:0] PrivilegedNextPCM,
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input logic InvalidateICacheM,
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output logic [31:0] InstrD, InstrM,
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output logic [`XLEN-1:0] PCM,
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// branch predictor
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output logic [4:0] InstrClassM,
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output logic BPPredDirWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic BPPredClassNonCFIWrongM,
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// Faults
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input logic IllegalBaseInstrFaultD,
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output logic ITLBInstrPageFaultF,
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output logic IllegalIEUInstrFaultD,
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output logic InstrMisalignedFaultM,
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output logic [`XLEN-1:0] InstrMisalignedAdrM,
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input logic ExceptionM, PendingInterruptM,
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// mmu management
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PTE,
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input logic [1:0] PageType,
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic ITLBWriteF, ITLBFlushF,
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output logic ITLBMissF,
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output logic InstrAccessFaultF
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output logic InstrAccessFaultF
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);
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logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
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@ -95,73 +88,85 @@ module ifu (
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logic [31:0] InstrE;
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logic [`XLEN-1:0] PCD;
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic reset_q; // *** look at this later.
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logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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logic [`XLEN-1:0] PCBPWrongInvalidate;
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logic BPPredWrongM;
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(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
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logic [`XLEN+1:0] PCFExt;
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logic [`XLEN-1:0] PCBPWrongInvalidate;
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logic BPPredWrongM;
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logic CacheableF;
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logic [11:0] PCNextFMux;
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logic [`XLEN-1:0] PCFMux;
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logic [`XLEN-1:0] PCFp2;
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logic SelNextSpill, SelSpill, SpillSave;
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logic Spill;
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logic SelNextSpill;
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logic ICacheFetchLine;
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logic BusStall;
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logic ICacheStallF;
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logic IgnoreRequest;
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logic CPUBusy;
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logic [31:0] PostSpillInstrRawF;
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generate
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if(`C_SUPPORTED) begin : SpillSupport
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logic [`XLEN-1:0] PCFp2;
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logic Spill;
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logic SelSpill, SpillSave;
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logic [15:0] SpillDataBlock0;
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// this exists only if there are compressed instructions.
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assign PCFp2 = PCF + `XLEN'b10;
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logic [15:0] SpillDataBlock0;
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logic [31:0] PostSpillInstrRawF;
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assign PCFp2 = PCF + `XLEN'b10;
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assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0];
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assign PCFMux = SelSpill ? PCFp2 : PCF;
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assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0];
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assign PCFMux = SelSpill ? PCFp2 : PCF;
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assign Spill = &PCF[$clog2(`ICACHE_BLOCKLENINBITS/32)+1:1];
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assign Spill = &PCF[$clog2(`ICACHE_BLOCKLENINBITS/32)+1:1];
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typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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always_ff @(posedge clk)
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if (reset) CurrState <= #1 STATE_SPILL_READY;
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else CurrState <= #1 NextState;
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always_ff @(posedge clk)
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if (reset) CurrState <= #1 STATE_SPILL_READY;
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else CurrState <= #1 NextState;
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always_comb begin
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case(CurrState)
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STATE_SPILL_READY: if (Spill & ~(ICacheStallF | BusStall)) NextState = STATE_SPILL_SPILL;
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else NextState = STATE_SPILL_READY;
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STATE_SPILL_SPILL: if(ICacheStallF | BusStall | StallF) NextState = STATE_SPILL_SPILL;
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else NextState = STATE_SPILL_READY;
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default: NextState = STATE_SPILL_READY;
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endcase
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end
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always_comb begin
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case(CurrState)
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STATE_SPILL_READY: if (Spill & ~(ICacheStallF | BusStall)) NextState = STATE_SPILL_SPILL;
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else NextState = STATE_SPILL_READY;
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STATE_SPILL_SPILL: if(ICacheStallF | BusStall | StallF) NextState = STATE_SPILL_SPILL;
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else NextState = STATE_SPILL_READY;
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default: NextState = STATE_SPILL_READY;
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endcase
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end
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assign SelSpill = CurrState == STATE_SPILL_SPILL;
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assign SelNextSpill = (CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall))) |
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(CurrState == STATE_SPILL_SPILL & (ICacheStallF | BusStall));
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assign SpillSave = CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall));
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assign SelSpill = CurrState == STATE_SPILL_SPILL;
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assign SelNextSpill = (CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall))) |
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(CurrState == STATE_SPILL_SPILL & (ICacheStallF | BusStall));
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assign SpillSave = CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall));
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flopenr #(16) SpillInstrReg(.clk(clk),
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.en(SpillSave),
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.reset(reset),
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.d(InstrRawF[15:0]),
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.q(SpillDataBlock0));
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flopenr #(16) SpillInstrReg(.clk(clk),
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.en(SpillSave),
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.reset(reset),
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.d(InstrRawF[15:0]),
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.q(SpillDataBlock0));
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assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataBlock0} : InstrRawF;
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assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
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assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataBlock0} : InstrRawF;
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assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
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// end of spill support
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end else begin : NoSpillSupport // block: SpillSupport
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assign PCNextFMux = PCNextF[11:0];
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assign PCFMux = PCF;
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assign SelNextSpill = 0;
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assign PostSpillInstrRawF = InstrRawF;
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end
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endgenerate
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assign PCFExt = {2'b00, PCFMux};
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@ -254,15 +259,13 @@ module ifu (
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endgenerate
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// select between dcache and direct from the BUS. Always selected if no dcache.
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// handled in the busfsm.
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mux2 #(32) UnCachedInstrMux(.d0(FinalInstrRawF),
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.d1(ICacheMemWriteData[31:0]),
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.s(SelUncachedAdr),
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.y(InstrRawF));
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// always present
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genvar index;
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generate
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for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
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@ -292,9 +295,6 @@ module ifu (
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// uses interlock fsm.
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assign IgnoreRequest = ITLBMissF;
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
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