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Fixed a bug where the instruction fetch got out of sync with the icache.

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This commit is contained in:
Ross Thompson 2022-01-03 13:27:15 -06:00
parent d909e8f371
commit e0c310fea7
2 changed files with 5 additions and 1 deletions
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3
wally-pipelined/src/cache/icachefsm.sv vendored
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@ -128,6 +128,9 @@ module icachefsm
STATE_READY: begin
SelAdr = 2'b00;
ICacheReadEn = 1'b1;
if(IgnoreRequest) begin
NextState = STATE_READY;
end else
if(ITLBMissF) begin
NextState = STATE_READY;
SelAdr = 2'b01;

3
wally-pipelined/src/ifu/ifu.sv
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@ -244,7 +244,8 @@ module ifu (
assign IfuStallF = ICacheStallF | BusStall;
assign IgnoreRequest = ITLBMissF | ExceptionM | PendingInterruptM;
//assign IgnoreRequest = ITLBMissF | ExceptionM | PendingInterruptM;
assign IgnoreRequest = ITLBMissF;