167 Commits

Author	SHA1	Message	Date
Ross Thompson	4273775a2b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 14:22:19 -06:00
Ross Thompson	e02bc8db67	rv32e works for now. Still need to optimize.	2022-02-08 14:21:55 -06:00
Ross Thompson	f211fe635a	Moved some muxes back into the bp.	2022-02-08 14:17:44 -06:00
David Harris	1479762ae9	RAM simplification	2022-02-08 20:15:23 +00:00
Ross Thompson	aa12d90272	Temporary commit which gets the no branch predictor implementation working.	2022-02-08 14:13:55 -06:00
Ross Thompson	8a2ee22395	Finished merge.	2022-02-08 11:36:24 -06:00
Ross Thompson	e2191e3637	Preparing to make a major change to the cache's write enables.	2022-02-08 09:47:01 -06:00
David Harris	c61cd55c5c	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
Ross Thompson	5c9e23527d	cachefsm cleanup.	2022-02-07 22:09:56 -06:00
Ross Thompson	da2dca9816	Removed VDWriteEnable.	2022-02-07 21:59:18 -06:00
Ross Thompson	161f907cae	more partial cleanup of fsm and write enables.	2022-02-07 17:41:56 -06:00
Ross Thompson	359a23237d	Progress towards simplifying the cache's write enables.	2022-02-07 17:23:09 -06:00
Ross Thompson	188fe28691	more cleanup.	2022-02-07 13:29:19 -06:00
Ross Thompson	9510a33c15	More cachefsm cleanup.	2022-02-07 13:19:37 -06:00
Ross Thompson	708e0cf183	More cachefsm cleanup.	2022-02-07 12:30:27 -06:00
Ross Thompson	5539a5fa6f	More cachefsm cleanup.	2022-02-07 11:16:20 -06:00
Ross Thompson	6668956351	More cachefsm cleanup.	2022-02-07 11:12:28 -06:00
Ross Thompson	5536e3ca90	More cachefsm cleanup.	2022-02-07 10:54:22 -06:00
Ross Thompson	529d8b629a	Cache cleanup.	2022-02-07 10:43:58 -06:00
Ross Thompson	41a79556e0	More cachfsm cleanup.	2022-02-07 10:33:50 -06:00
David Harris	99f3d7a7f6	Reverted cache change	2022-02-07 14:47:20 +00:00
David Harris	45dc9c1ae6	Cache syntax cleanup	2022-02-07 14:43:24 +00:00
Ross Thompson	0b66106925	More cachefsm cleanup.	2022-02-06 21:50:44 -06:00
Ross Thompson	dd6baa9ed4	started cachefsm cleanup.	2022-02-06 21:39:38 -06:00
David Harris	9b55848ffc	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
Ross Thompson	d21be9d998	Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.	2022-02-04 23:49:07 -06:00
Ross Thompson	ea84211ff9	Removed unused ports from caches and buses.	2022-02-04 22:52:51 -06:00
Ross Thompson	011ad09341	Cleanup.	2022-02-04 22:40:51 -06:00
Ross Thompson	4074f695e0	Moved the hwdata mux back into the busdp.	2022-02-04 22:39:13 -06:00
Ross Thompson	40eb055861	Merged together the two sub cache line read muxes. ... One mux was used for loads and the other for eviction.	2022-02-04 22:30:04 -06:00
David Harris	72bc64ef28	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
Ross Thompson	290430cda8	Moved the sub cache line read logic to lsu/ifu.	2022-02-04 20:42:53 -06:00
Ross Thompson	725852362e	Got separate module for the sub cache line read.	2022-02-04 20:23:09 -06:00
Ross Thompson	cdd599e340	Second optimization of save/restore.	2022-02-04 14:35:12 -06:00
Ross Thompson	459054900f	Optimization of cache save/restore.	2022-02-04 14:21:04 -06:00
Ross Thompson	7c1f7e335c	Working first cut of the cache changes moving the replay to a save/restore. ... The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.	2022-02-04 13:31:32 -06:00
David Harris	ee3300bcd2	sram1rw cleanup	2022-02-03 18:03:22 +00:00
David Harris	97d31cec21	sram1rw cleanup	2022-02-03 17:50:23 +00:00
David Harris	f9dd79d3e3	cachereplacementpolicy cleanup	2022-02-03 17:19:14 +00:00
David Harris	034ff5462c	cachereplacementpolicy cleanup	2022-02-03 17:18:48 +00:00
David Harris	65f3bf4e0a	cacheway cleanup	2022-02-03 16:52:22 +00:00
David Harris	eef04eed84	cacheway cleanup	2022-02-03 16:33:01 +00:00
David Harris	4d09510af9	cacheway cleanup	2022-02-03 16:07:55 +00:00
David Harris	7f237220dd	cacheway cleanup	2022-02-03 16:00:57 +00:00
David Harris	a6708ed887	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	38bbe23d14	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	02071700d6	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	6c5b0bec40	More cleanup of IFU.	2022-02-01 14:32:27 -06:00
Ross Thompson	1f0821da0d	IFU and LSU now share the same busdp module.	2022-01-31 16:25:41 -06:00