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Working first cut of the cache changes moving the replay to a save/restore.

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The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
This commit is contained in:
Ross Thompson 2022-02-04 13:31:32 -06:00
parent ee3300bcd2
commit 7c1f7e335c
3 changed files with 96 additions and 71 deletions
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9
pipelined/src/cache/cache.sv vendored
View File

@ -105,8 +105,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
logic LRUWriteEn;
logic [NUMWAYS-1:0] VDWriteEnableWay;
logic SelFlush;
logic ResetOrFlushAdr, ResetOrFlushWay;
logic ResetOrFlushAdr, ResetOrFlushWay;
logic save, restore;
/////////////////////////////////////////////////////////////////////////////////////////////
// Read Path
/////////////////////////////////////////////////////////////////////////////////////////////
@ -125,7 +126,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
.WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMLineWayWriteEnable),
.WriteData(SRAMWriteData),
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .Victim(VictimWay), .Flush(FlushWay), .SelFlush,
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .Victim(VictimWay), .Flush(FlushWay),
.save, .restore, .SelFlush,
.SelectedReadDataLine(ReadDataLineWay), .WayHit, .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay),
.InvalidateAll(InvalidateCacheM));
if(NUMWAYS > 1) begin:vict
@ -213,5 +215,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
.SRAMLineWriteEnable, .SelEvict, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
.save, .restore,
.VDWriteEnable, .LRUWriteEn);
endmodule

83
pipelined/src/cache/cachefsm.sv vendored
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@ -32,49 +32,51 @@
module cachefsm
(input logic clk,
input logic reset,
input logic reset,
// inputs from IEU
input logic [1:0] RW,
input logic [1:0] Atomic,
input logic FlushCache,
input logic FlushCache,
// hazard inputs
input logic CPUBusy,
input logic CPUBusy,
// interlock fsm
input logic IgnoreRequest,
input logic IgnoreRequest,
// Bus inputs
input logic CacheBusAck,
input logic CacheBusAck,
// dcache internals
input logic CacheHit,
input logic VictimDirty,
input logic FlushAdrFlag,
input logic FlushWayFlag,
input logic CacheHit,
input logic VictimDirty,
input logic FlushAdrFlag,
input logic FlushWayFlag,
// hazard outputs
output logic CacheStall,
output logic CacheStall,
// counter outputs
output logic CacheMiss,
output logic CacheAccess,
output logic CacheMiss,
output logic CacheAccess,
// Bus outputs
output logic CacheCommitted,
output logic CacheWriteLine,
output logic CacheFetchLine,
output logic CacheCommitted,
output logic CacheWriteLine,
output logic CacheFetchLine,
// dcache internals
output logic [1:0] SelAdr,
output logic SetValid,
output logic ClearValid,
output logic SetDirty,
output logic ClearDirty,
output logic SRAMWordWriteEnable,
output logic SRAMLineWriteEnable,
output logic SelEvict,
output logic LRUWriteEn,
output logic SelFlush,
output logic FlushAdrCntEn,
output logic FlushWayCntEn,
output logic FlushAdrCntRst,
output logic FlushWayCntRst,
output logic VDWriteEnable
output logic SetValid,
output logic ClearValid,
output logic SetDirty,
output logic ClearDirty,
output logic SRAMWordWriteEnable,
output logic SRAMLineWriteEnable,
output logic SelEvict,
output logic LRUWriteEn,
output logic SelFlush,
output logic FlushAdrCntEn,
output logic FlushWayCntEn,
output logic FlushAdrCntRst,
output logic FlushWayCntRst,
output logic save,
output logic restore,
output logic VDWriteEnable
);
@ -141,7 +143,8 @@ module cachefsm
NextState = STATE_READY;
CacheFetchLine = 1'b0;
CacheWriteLine = 1'b0;
save = 1'b0;
restore = 1'b0;
case (CurrState)
STATE_READY: begin
@ -178,7 +181,8 @@ module cachefsm
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
PreSelAdr = 2'b01;
//PreSelAdr = 2'b01;
save = 1'b1;
end
else begin
SRAMWordWriteEnable = 1'b1;
@ -194,7 +198,8 @@ module cachefsm
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
//PreSelAdr = 2'b01;
save = 1'b1;
end
else begin
NextState = STATE_READY;
@ -210,7 +215,8 @@ module cachefsm
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
//PreSelAdr = 2'b01;
save = 1'b1;
end
else begin
NextState = STATE_READY;
@ -278,6 +284,7 @@ module cachefsm
PreSelAdr = 2'b01;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
save = 1'b1;
end
else begin
SRAMWordWriteEnable = 1'b1;
@ -289,7 +296,8 @@ module cachefsm
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
//PreSelAdr = 2'b01;
save = 1'b1;
end
else begin
NextState = STATE_READY;
@ -304,7 +312,8 @@ module cachefsm
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
//PreSelAdr = 2'b01;
save = 1'b1;
end
else begin
NextState = STATE_READY;
@ -325,9 +334,10 @@ module cachefsm
STATE_CPU_BUSY: begin
PreSelAdr = 2'b00;
restore = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01;
//PreSelAdr = 2'b01;
end
else begin
NextState = STATE_READY;
@ -339,6 +349,7 @@ module cachefsm
SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
restore = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
end

75
pipelined/src/cache/cacheway.sv vendored
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@ -32,51 +32,52 @@
module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (
input logic clk,
input logic reset,
input logic clk,
input logic reset,
input logic [$clog2(NUMLINES)-1:0] RAdr,
input logic [`PA_BITS-1:0] PAdr,
input logic WriteEnable,
input logic VDWriteEnable,
input logic [LINELEN/`XLEN-1:0] WriteWordEnable,
input logic TagWriteEnable,
input logic [LINELEN-1:0] WriteData,
input logic SetValid,
input logic ClearValid,
input logic SetDirty,
input logic ClearDirty,
input logic SelEvict,
input logic Victim,
input logic InvalidateAll,
input logic SelFlush,
input logic Flush,
input logic [$clog2(NUMLINES)-1:0] RAdr,
input logic [`PA_BITS-1:0] PAdr,
input logic WriteEnable,
input logic VDWriteEnable,
input logic [LINELEN/`XLEN-1:0] WriteWordEnable,
input logic TagWriteEnable,
input logic [LINELEN-1:0] WriteData,
input logic SetValid,
input logic ClearValid,
input logic SetDirty,
input logic ClearDirty,
input logic SelEvict,
input logic Victim,
input logic InvalidateAll,
input logic SelFlush,
input logic Flush,
input logic save, restore,
output logic [LINELEN-1:0] SelectedReadDataLine,
output logic WayHit,
output logic VictimDirty,
output logic [TAGLEN-1:0] VictimTag);
output logic [LINELEN-1:0] SelectedReadDataLine,
output logic WayHit,
output logic VictimDirty,
output logic [TAGLEN-1:0] VictimTag);
logic [NUMLINES-1:0] ValidBits;
logic [NUMLINES-1:0] DirtyBits;
logic [LINELEN-1:0] ReadDataLine;
logic [TAGLEN-1:0] ReadTag;
logic Valid;
logic Dirty;
logic [LINELEN-1:0] ReadDataLine, ReadDataLineRaw, ReadDataLineSaved;
logic [TAGLEN-1:0] ReadTag, ReadTagRaw, ReadTagSaved;
logic Valid, ValidRaw, ValidSaved;
logic Dirty, DirtyRaw, DirtySaved;
logic SelData;
logic SelTag;
logic SelTag;
logic [$clog2(NUMLINES)-1:0] RAdrD;
logic SetValidD, ClearValidD;
logic SetDirtyD, ClearDirtyD;
logic WriteEnableD, VDWriteEnableD;
/////////////////////////////////////////////////////////////////////////////////////////////
// Tag Array
/////////////////////////////////////////////////////////////////////////////////////////////
sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk),
.Adr(RAdr), .ReadData(ReadTag),
.Adr(RAdr), .ReadData(ReadTagRaw),
.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable));
// AND portion of distributed tag multiplexer
@ -92,7 +93,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
genvar words;
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr),
.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
.ReadData(ReadDataLineRaw[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
end
@ -115,7 +116,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
flop #(4) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable, VDWriteEnable},
{SetValidD, ClearValidD, WriteEnableD, VDWriteEnableD});
assign Valid = ValidBits[RAdrD];
assign ValidRaw = ValidBits[RAdrD];
/////////////////////////////////////////////////////////////////////////////////////////////
// Dirty Bits
@ -129,8 +130,18 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b0;
end
flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
assign Dirty = DirtyBits[RAdrD];
assign DirtyRaw = DirtyBits[RAdrD];
flopenr #(1) cachedirtysavereg(clk, reset, save, DirtyRaw, DirtySaved);
mux2 #(1) saverestoredirtymux(DirtyRaw, DirtySaved, restore, Dirty);
end else assign Dirty = 1'b0;
// save restore option of handling cpu busy
flopen #(TAGLEN+LINELEN) cachereadsavereg(clk, save, {ReadTagRaw, ReadDataLineRaw}, {ReadTagSaved, ReadDataLineSaved});
flopenr #(1) cachevalidsavereg(clk, reset, save, ValidRaw, ValidSaved);
mux2 #(1+TAGLEN+LINELEN) saverestoremux({ValidRaw, ReadTagRaw, ReadDataLineRaw}, {ValidSaved, ReadTagSaved, ReadDataLineSaved},
restore, {Valid, ReadTag, ReadDataLine});
endmodule