Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

RAM simplification

Browse Source
This commit is contained in:
David Harris 2022-02-08 20:15:23 +00:00
parent 510b47523a
commit 1479762ae9
2 changed files with 9 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
pipelined/src/cache/sram1rw.sv vendored
View File

@ -46,6 +46,7 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
logic WriteEnableD;
//*** model as single port
// *** merge with simpleram
always_ff @(posedge clk) begin
AddrD <= Adr;
WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay. Implement alternative cache stall to avoid this. Eliminates a bunch of delay flops elsewhere

20
pipelined/src/generic/flop/simpleram.sv
View File

@ -40,18 +40,14 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
/* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw
always_ff @(posedge clk) begin
rd <= RAM[a[31:3]];
if (we) RAM[a[31:3]] <= #1 wd;
end
end else begin
always_ff @(posedge clk) begin:ramrw
rd <= RAM[a[31:2]];
if (we) RAM[a[31:2]] <= #1 wd;
end
// discard bottom 2 or 3 bits of address offset within word or doubleword
localparam adrlsb = (`XLEN==64) ? 3 : 2;
logic [31:adrlsb] adrmsbs;
assign adrmsbs = a[31:adrlsb];
always_ff @(posedge clk) begin
rd <= RAM[adrmsbs];
if (we) RAM[adrmsbs] <= #1 wd;
end
/* verilator lint_on WIDTH */
endmodule