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Author	SHA1	Message	Date
David Harris	6fd32b6643	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-19 06:49:25 -08:00
David Harris	887cf935dc	wallySynthAll.sh automates running all synthesis experiments without maxopt	2023-11-19 06:49:07 -08:00
David Harris	b692c913c4	Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile	2023-11-18 20:56:50 -08:00
David Harris	acd8a63628	Merge pull request #489 from ross144/main ... fixes issue #487	2023-11-18 19:22:33 -08:00
Rose Thompson	4ad7afcbf2	Merge pull request #488 from JacobPease/main ... FPGA Bootloader Preload From File	2023-11-18 17:24:52 -08:00
Jacob Pease	a1e7158bd9	Merge branch 'main' of github.com:openhwgroup/cvw	2023-11-18 19:20:48 -06:00
Jacob Pease	87e6a5ccf2	Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.	2023-11-18 19:15:39 -06:00
Rose Thompson	efcd09c6cd	Merge branch 'main' of github.com:ross144/cvw	2023-11-18 19:01:48 -06:00
Rose Thompson	8cbd3de413	Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.	2023-11-18 19:01:39 -06:00
Rose Thompson	4429732e8f	Merge pull request #485 from davidharrishmc/dev ... Wally sweep running again, embench sweep across configs	2023-11-17 21:42:12 -08:00
David Harris	acc2db256f	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
David Harris	96556064a4	Restored RV64GC BPRED_SIZE=10 for consistent synthesis results	2023-11-17 18:31:44 -08:00
David Harris	423ae2bb76	Ignore benchmark results	2023-11-17 17:02:32 -08:00
David Harris	96f9409da4	Embench Makefile to sweep experiments across configs	2023-11-17 15:11:52 -08:00
David Harris	7b33331cf7	Got Wally sweep running again	2023-11-17 15:10:57 -08:00
David Harris	c500a7c057	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-17 14:26:55 -08:00
David Harris	0eb23569f5	Merge pull request #480 from stineje/main ... wrapper insertion automatically for Wally vs. individual PPA analysis	2023-11-17 14:26:47 -08:00
James E. Stine	3dc7b93f57	Revert removal of WRAPPER option that is not prudent	2023-11-17 16:25:35 -06:00
David Harris	44ec6efdab	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-17 13:28:07 -08:00
David Harris	f4f389f373	Initial version of embench_arch_sweep.py	2023-11-17 13:27:57 -08:00
David Harris	70c58a8ce1	Merge pull request #484 from ross144/main ... Changed bpred-sim.py to only simulate 12 jobs at once.	2023-11-17 13:26:24 -08:00
Rose Thompson	8cf2c404bf	bpred-sim only simulates 12 jobs at once.	2023-11-17 15:21:58 -06:00
David Harris	8baa5b2e7b	Merge pull request #483 from ross144/main ... Fixed branch predictor embench generation results	2023-11-17 10:07:30 -08:00
Rose Thompson	d95d7130a3	Fixed bugs in paraseHPMC.py	2023-11-17 12:05:22 -06:00
Rose Thompson	38b327eaf8	Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters.	2023-11-17 11:21:25 -06:00
Jacob Pease	38cf7f0fb7	ahbsdc submodule actually added this time.	2023-11-16 17:46:48 -06:00
Jacob Pease	9df87872ef	Deleted vivado-risc-v directory and added ahbsdc.	2023-11-16 15:13:12 -06:00
Jacob Pease	23e5fca2a7	Merge branch 'main' of github.com:jacobpease/cvw	2023-11-16 14:04:11 -06:00
Jacob Pease	ff73f798ed	Replaced vivado-risc-v addins directory with new SDC repo.	2023-11-16 13:59:12 -06:00
Rose Thompson	0b49c736b9	Removed the size opt tests from the branch predictor analysis.	2023-11-15 22:35:33 -06:00
David Harris	94201e993f	Merge pull request #481 from ross144/main ... Fixed the BTB logger so sim_bp correctly reports BTB performance	2023-11-15 17:45:38 -08:00
Rose Thompson	21b2a71bd6	Updates to btb logger processing.	2023-11-15 16:53:44 -06:00
Rose Thompson	c4f4e0fbc0	Added btb reference data.	2023-11-15 16:39:35 -06:00
Rose Thompson	9a90c15f37	Extended SeparateBranch to support both just branches and all control flow instructions.	2023-11-15 16:36:49 -06:00
Rose Thompson	bc935b1b3b	Fixed second bug in the logger script when branch logging enabled but counter logger not.	2023-11-15 14:56:02 -06:00
Rose Thompson	5d4a89b27c	Fixed bug in the btb branch logging. ... We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.	2023-11-15 14:51:47 -06:00
David Harris	7b2bb86ced	changed to head of riscv-arch-test	2023-11-15 09:48:13 -08:00
Rose Thompson	dc8502899c	Merge pull request #479 from davidharrishmc/main ... Removed and added back in riscv-arch-test to try to fix corruption	2023-11-15 08:46:42 -08:00
Rose Thompson	663eb9a17d	Merge pull request #478 from davidharrishmc/dev ... Removed non-functioning Zfh from rv64gc	2023-11-15 08:46:24 -08:00
David Harris	eef39bd495	Fixed typo in lsu parameter	2023-11-15 08:30:48 -08:00
David Harris	817ddbc7c5	Adjusted LSU misaligned buffer to fix synthesis warning	2023-11-15 08:19:50 -08:00
David Harris	cfaeeae25a	Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter	2023-11-15 08:15:01 -08:00
David Harris	dc3e412c62	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-15 08:06:35 -08:00
David Harris	98176665de	Fixed messed-up hazard.sv	2023-11-15 08:05:41 -08:00
James E. Stine	8ca1e3ba37	missing synth.tcl added for use with wrapper	2023-11-15 08:48:07 -06:00
James E. Stine	79d6fe8c93	Add wrapper passing automatically for individual designs vs. Wally	2023-11-15 08:45:25 -06:00
David Harris	20afaa558a	Added back in riscv-arch-test	2023-11-15 06:07:57 -08:00
David Harris	1c4b3e37b1	Removed riscv-arch-test submodule that was corrupted	2023-11-15 06:05:55 -08:00
David Harris	90cf128349	Added back riscv-arch-test fresh	2023-11-15 05:48:33 -08:00
David Harris	18c29dd7d0	Removed riscv-arch-test submodule that appears corrupted	2023-11-15 05:46:38 -08:00