33 Commits

Author	SHA1	Message	Date
Katherine Parry	62205ebb3b	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
David Harris	72e216d053	APB CLINT passing regression	2022-07-05 15:51:35 +00:00
Katherine Parry	8f98f3bfab	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
Katherine Parry	03d823f5d7	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
Katherine Parry	5f7072bd96	postprocessing unit created and passing all tests	2022-06-13 22:47:51 +00:00
slmnemo	be658d3933	Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors	2022-06-08 15:03:15 -07:00
slmnemo	a5aa75e5de	Merge branch 'main' into cacheburstmode	2022-06-08 02:21:33 +00:00
slmnemo	1d22fc707a	Added lock signal to ensure AHB speaks with the right bus	2022-06-08 02:19:21 +00:00
slmnemo	90c5e5d319	Reworked bus to handle burst interfacing	2022-06-07 11:22:53 +00:00
David Harris	9065b684f8	Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit	2022-06-02 09:37:59 -07:00
David Harris	129fab3794	Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.	2022-06-02 14:18:55 +00:00
slmnemo	efce3e4953	added LSUBurstDone signal to signal when a burst has finished	2022-05-26 16:29:13 -07:00
slmnemo	80965f953c	added burst size signals to the IFU, EBU, LSU, and busdp	2022-05-25 18:02:50 -07:00
David Harris	4c5e361b00	More unused signal cleanup	2022-05-12 15:26:08 +00:00
David Harris	5acb526375	More unused signal cleanup	2022-05-12 15:21:09 +00:00
David Harris	fb725a9e0a	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	2cdd49c7d2	WFI terminates when an interrupt is pending even if interrupts are globally disabled	2022-05-08 04:30:46 +00:00
David Harris	7024293a59	Zero'd wfiM when ZICSR not supported to fix hang in E tests	2022-05-05 15:32:13 +00:00
David Harris	94459ade3d	Changed WFI to stall pipeline in memory stage	2022-05-05 02:03:44 +00:00
David Harris	9c4de0e9c1	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
Kip Macsai-Goren	7bc6943527	Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)	2022-04-22 22:46:11 +00:00
Ross Thompson	5ef6cde52e	Added more ILA signals.	2022-04-02 16:39:45 -05:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
bbracker	46ffa4b079	fix typo that Madeleine found	2022-03-28 15:39:29 -07:00
bbracker	150a7b234b	tabs vs spaces disagreement	2022-03-24 17:11:41 -07:00
bbracker	9f60256f22	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
Ross Thompson	58668812c1	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
Ross Thompson	62f5f1e622	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	1bb8d36308	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00