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mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Commit Graph

677 Commits

Author SHA1 Message Date
Ross Thompson
40e7cda84a Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
719b00e338 Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
69d520a7eb Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
cd68896637 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
8193946996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
05484c4c05 signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
27e32980ad cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
17ae1a1b1b cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
abc79c6c8e Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Katherine Parry
655e2d3810 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Katherine Parry
b3d932cd61 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
David Harris
d22587090b Reset MSR on read 2022-07-22 04:29:27 +00:00
slmnemo
3d2c6683d8 Fixed UART bug related to parity and MSR/LSR 2022-07-21 20:35:46 -07:00
Katherine Parry
fbe8bb2298 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
7950a675ea added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Katherine Parry
a30d9c6bd8 turn off 2 word store durring non-fp instructions 2022-07-20 21:57:23 +00:00
Ross Thompson
1cad05fef9 Minor cleanup of cache. 2022-07-19 23:04:23 -05:00
Ross Thompson
8698799077 Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction. 2022-07-19 22:42:25 -05:00
Katherine Parry
b26297e874 moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
cturek
0f94177765 small changes 2022-07-20 01:36:25 +00:00
Katherine Parry
d61f84e751 oprimized zeros and replaced complex ?: with always_comb 2022-07-19 23:44:37 +00:00
Ross Thompson
a79e5e11f6 Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Katherine Parry
514674417e moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
64b3e4117b reworked fmashiftcalc to match book 2022-07-19 00:04:24 +00:00
David Harris
9fd772ce83 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 23:11:12 +00:00
Katherine Parry
cce5fb8dfd moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
7268b4b334 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
d6f1fc12db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 17:31:29 +00:00
Katherine Parry
0210718f19 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Ross Thompson
0ef6137ab9 Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
8356e5d742 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
David Harris
03f573351a Rewrote convert shift calculation with always for ease of reading 2022-07-17 16:40:58 +00:00
David Harris
622773343f restored intPending logic to be sticky for PLIC 2022-07-16 17:43:31 -07:00
Katherine Parry
e3ed40620c forgot some files 2022-07-15 21:42:45 +00:00
Katherine Parry
5cb9c9f319 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
Katherine Parry
2fe8b6e34c fixed error in divsqrt 2022-07-14 18:16:00 +00:00
Katherine Parry
66bef379cb renamed a file to fit diagram 2022-07-13 23:44:54 +00:00
Katherine Parry
3dcddf8453 some code cleanup 2022-07-13 15:28:22 -07:00
Katherine Parry
b874c5c05d removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
Katherine Parry
b45b3baec2 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
3c1bea1104 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
12a54161c0 found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
18d7fee541 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
1267d33d3c forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
ba339fc794 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
bea4ec078d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
David Harris
03a20610aa added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
d1a7832dd9 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00