Ross Thompson
40bdcda32d
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Ross Thompson
668a79cf77
Updated benchmarking code.
2021-05-27 11:48:29 -05:00
Ross Thompson
735e511073
fixed bug with icache miss spill fsm branch.
2021-05-25 14:26:22 -05:00
Ross Thompson
aa9a81b760
Merge remote-tracking branch 'refs/remotes/origin/main' into main
2021-05-24 23:25:36 -05:00
Ross Thompson
13034c7406
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
2021-05-24 23:24:54 -05:00
James E. Stine
bbc1dfb309
Minor cosmetic elements on div.sv
2021-05-24 19:30:28 -05:00
James E. Stine
1704fdc877
Mod for DIV/REM instruction and update to div.sv unit
2021-05-24 19:29:13 -05:00
bbracker
82a6ee4c0e
slightly more path independence for using verilator
2021-05-24 18:11:56 -04:00
bbracker
d7405e476e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-24 17:09:14 -04:00
bbracker
7e2073e482
peripheral testing standardization
2021-05-24 17:08:40 -04:00
Ross Thompson
3c5e87d6c2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-24 14:28:41 -05:00
Katherine Parry
03aea055fa
FMV.X.D imperas test passes
2021-05-24 14:44:30 -04:00
Ross Thompson
dd26b754eb
Fixed minor bug in instruction class decoding.
2021-05-24 13:41:14 -05:00
Ross Thompson
b06fda88ff
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
2021-05-24 12:37:16 -05:00
Ross Thompson
daf344f1ba
Updated branch predictor tests/benchmarks.
2021-05-24 11:13:33 -05:00
James E. Stine
194c32defa
Update header for FPadd
2021-05-24 08:28:16 -05:00
Katherine Parry
55f22979ca
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
bbracker
142b02b30a
improved PLIC test organization
2021-05-21 15:13:02 -04:00
James E. Stine
49a4097d97
Minor testbench updates to rv64icfd
2021-05-21 09:41:21 -05:00
James E. Stine
47487a625f
Update to testbench-imperase for rv64icfd
2021-05-21 09:28:44 -05:00
James E. Stine
694e21541b
Update to FLD/FSD testbench
2021-05-21 09:26:55 -05:00
James E. Stine
474d479280
Update to rv64icfd wally-config to run through FP tests
2021-05-21 09:22:17 -05:00
Katherine Parry
67a41748ba
FMV.D.X imperas test passes
2021-05-20 22:18:33 -04:00
Katherine Parry
71e4a10efb
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
114bba8370
small bit of busybear debug progress
2021-05-19 20:18:00 -04:00
bbracker
8554f2f3cd
plic implementation optimizations
2021-05-19 18:10:48 +00:00
bbracker
fd4fae0406
commented out MSTATUS test
2021-05-19 12:38:01 -04:00
James E. Stine
058b265d18
Update rv64icfd batch script
2021-05-18 16:01:53 -05:00
James E. Stine
f407bee5ae
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
2021-05-18 13:48:44 -05:00
bbracker
18ab9015f9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-18 14:33:40 -04:00
bbracker
f43ea946aa
changed lint script to use absolute path for verilator because cron jobs stink at using paths
2021-05-18 14:33:22 -04:00
David Harris
7dcc53dcf5
fixed rv64mmu makefile
2021-05-18 14:25:55 -04:00
David Harris
5f214d60b6
Removed rv64wally
2021-05-18 14:08:46 -04:00
David Harris
433ea61d9e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
2021-05-18 14:01:19 -04:00
bbracker
9b3332f3c3
commented changes to imperas makefiles
2021-05-18 13:34:48 -04:00
Katherine Parry
409438bc95
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
bbracker
c08f5e6732
script for running make and logging output
2021-05-17 22:12:18 -04:00
bbracker
31c29b0cf1
changed makefiles so that make stops at bad source code that does not compile
2021-05-17 21:20:30 -04:00
bbracker
86d55cd07a
fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
2021-05-17 19:25:54 -04:00
bbracker
69ef758e78
regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
2021-05-17 18:44:47 -04:00
David Harris
1aa1908994
Deleted vish_stacktrace
2021-05-17 18:39:01 -04:00
David Harris
42483e5e03
Started MSTATUS tests
2021-05-17 18:37:56 -04:00
James E. Stine
49cc330bd9
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
Elizabeth Hedenberg
853c9243c1
commit ehedenberg coremark
2021-05-17 18:02:35 -04:00
Elizabeth Hedenberg
9d17950c1d
coremark commit ehedenberg final
2021-05-17 18:02:34 -04:00
James E. Stine
96eca3287f
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
James E. Stine
8822bdd6ad
Cleanup of regression
2021-05-17 16:58:15 -05:00
James E. Stine
41da78e0b6
Mod Imperas Testbench for updated Div/Rem
2021-05-17 16:56:30 -05:00
James E. Stine
97cbdae674
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
fda439b51e
Fix comment
2021-05-14 08:06:07 -04:00
