Ross Thompson
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a768c0406c
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Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed.
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2021-03-24 13:03:43 -05:00 |
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Domenico Ottolia
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3909158619
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re-organize privileged tests to be in rv64p to rv32p folders
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2021-03-24 13:51:25 -04:00 |
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Jarred Allen
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0776127c75
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Give some cache mem inputs a better name
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2021-03-24 12:31:50 -04:00 |
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Ross Thompson
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754f55c564
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Updated the .gitignore to reject all the extra compiled objects for the branchmarks.
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2021-03-24 10:30:19 -05:00 |
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Ross Thompson
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58487db60a
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Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack.
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2021-03-24 09:22:21 -05:00 |
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Jarred Allen
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abf9f3b3cb
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Fix compile errors from const not actually being constant (why does Verilog do this)
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2021-03-24 00:58:56 -04:00 |
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Ross Thompson
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ace39940b4
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Fixed RAS errors. Still some room for improvement with the BTB and RAS.
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2021-03-23 23:00:44 -05:00 |
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Jarred Allen
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1f01a12be9
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Merge branch 'main' into cache
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2021-03-23 23:35:36 -04:00 |
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Ross Thompson
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72d25d4443
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Fixed a bunch of bugs with the RAS.
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2021-03-23 21:49:16 -05:00 |
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Katherine Parry
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fb78dedae2
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fixed various bugs in the FMA
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2021-03-24 01:35:32 +00:00 |
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Ross Thompson
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c318606f05
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Fixed the valid bit issue. Now the branch predictor is actually predicting instructions.
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2021-03-23 20:20:23 -05:00 |
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Ross Thompson
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9d5c351340
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fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
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2021-03-23 20:06:45 -05:00 |
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Ross Thompson
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dee5d16850
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fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
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2021-03-23 16:53:48 -05:00 |
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Jarred Allen
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ebd2c60b74
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Begin work on direct-mapped cache
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2021-03-23 17:03:02 -04:00 |
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Teo Ene
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8556c07261
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Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem
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2021-03-23 15:21:13 -05:00 |
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Ross Thompson
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4836e8fe2c
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Simulation definitely shows the branch predictor counters and branch predictor don't work. :(
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2021-03-23 14:04:58 -05:00 |
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Ross Thompson
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c7e34bd4a0
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added a whole bunch of interseting test code for branches which does not work.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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c4f7c65210
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updated the branch predictor config.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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9909bdd4d5
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Added first benchmark.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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cebb2bc44d
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Temporary exe2memfile0.pl script to support starting addresses of 0.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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e6aef66853
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Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
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2021-03-23 13:54:59 -05:00 |
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Noah Boorstin
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355961f834
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busybear: more progress
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2021-03-23 14:49:30 -04:00 |
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Shreya Sanghai
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09b90557f7
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PC counts branch instructions
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2021-03-23 14:25:51 -04:00 |
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Jarred Allen
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c16605a105
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Remove deleted signal from waves
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2021-03-23 14:17:17 -04:00 |
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Noah Boorstin
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0dae5401f3
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busybear: more progress moving from instrf to instrrawd
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2021-03-23 14:06:21 -04:00 |
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Noah Boorstin
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7fb2ebec50
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busybear: ignore illegal instruction when starting
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2021-03-23 13:28:56 -04:00 |
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Jarred Allen
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789c189260
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Another tweak to regression-wally.py comments
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2021-03-23 00:18:38 -04:00 |
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Jarred Allen
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34cc9b4aeb
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Document some internal signals
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2021-03-23 00:10:35 -04:00 |
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Jarred Allen
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e4ebb4e31e
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Add comments explaining icache inputs
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2021-03-23 00:07:39 -04:00 |
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Jarred Allen
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2c4eda2ba3
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Slight change to regression-wally.py comments
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2021-03-23 00:02:40 -04:00 |
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Jarred Allen
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c47a80213e
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Small commit to see if new hook tests non-main branch
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2021-03-22 23:57:01 -04:00 |
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Noah Boorstin
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3c131bb2bd
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start migrating busybear over to InstrRawD/PCD
this breaks busybear for now
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2021-03-22 23:45:04 -04:00 |
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Noah Boorstin
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1592332d41
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Merge branch 'main' into cache
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2021-03-22 23:28:30 -04:00 |
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Noah Boorstin
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43d23e3d9b
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busybear: add better warning on illegal instruction
...also it seems that mret is being picked up as an illegal instruction??
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2021-03-22 18:24:35 -04:00 |
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Noah Boorstin
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4160bf50b0
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busybear: temporarially force rf[5] correct after failure to read CSR
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2021-03-22 18:12:41 -04:00 |
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Noah Boorstin
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4be19421c4
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busybear: allow overwriting read values
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2021-03-22 17:28:44 -04:00 |
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Noah Boorstin
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b4166e9fd0
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busybear: finally get the right error
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2021-03-22 16:52:22 -04:00 |
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bbracker
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c3a6d6bf42
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added delays to uart AHB signals
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2021-03-22 15:40:29 -04:00 |
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Jarred Allen
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307e33bc7e
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Remove DelaySideD since it isn't needed
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2021-03-22 15:13:23 -04:00 |
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Jarred Allen
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99fa8beef3
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Update icache interface
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2021-03-22 15:04:46 -04:00 |
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Noah Boorstin
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7350b9f18f
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busybear: comment out some debug printing
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2021-03-22 14:54:05 -04:00 |
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Jarred Allen
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507d8ed120
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Merge branch 'main' into cache
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2021-03-22 14:50:22 -04:00 |
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Noah Boorstin
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c4fb51fad1
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regression: expect 200k instead of 100k busybear instrs
and a minor busybear bugfix
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2021-03-22 14:47:52 -04:00 |
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Jarred Allen
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2269879459
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Merge branch 'main' into cache
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2021-03-22 13:47:48 -04:00 |
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bbracker
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eea7e2e47e
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first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
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Katherine Parry
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9af0ad815c
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fixed various bugs in the FMA
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2021-03-21 22:53:04 +00:00 |
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Jarred Allen
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bab0e3b90f
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Change busybear testbench to reflect new location of InstrF
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2021-03-20 18:20:27 -04:00 |
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Jarred Allen
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e32291bcc2
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Put Imperas testbench back
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2021-03-20 18:19:51 -04:00 |
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Jarred Allen
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066dc2caac
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Fix bug with PC incrementing
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2021-03-20 18:06:03 -04:00 |
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Jarred Allen
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e531a1b5ee
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Merge branch 'main' into cache
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2021-03-20 17:56:25 -04:00 |
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