Kip Macsai-Goren
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7bc6943527
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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bbracker
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5e76c83309
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deprecate unused LINUX_FIX_READ macro
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2022-04-21 19:14:47 -07:00 |
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bbracker
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afc38abe08
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change how tristate I/O is spoofed in GPIO loopback test
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2022-04-21 10:31:16 -07:00 |
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Ross Thompson
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8fcd4d47b7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-21 09:52:42 -05:00 |
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Ross Thompson
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165a36acac
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Modified wally-pipelined.do for no trace linux sim.
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2022-04-21 09:52:33 -05:00 |
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David Harris
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5c607f2b6b
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Simplified profile for UART boot; added warnings on UART Rx errors
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2022-04-21 04:54:45 +00:00 |
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Kip Macsai-Goren
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cd53163d9a
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added new tests to tests.vh
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2022-04-20 17:34:40 +00:00 |
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Kip Macsai-Goren
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080963c381
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fixed rv32ia to support clint and GPIO for priv tests
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2022-04-20 17:31:34 +00:00 |
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Kip Macsai-Goren
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510021af65
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added working general trap tests to regression
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2022-04-20 06:48:01 +00:00 |
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Ross Thompson
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546ef08eb2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-19 14:09:50 -05:00 |
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David Harris
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1f7a95637a
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Added baby torture tests
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2022-04-19 15:13:06 +00:00 |
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David Harris
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a8ad7be246
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Fixed WFI decoding in IFU
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2022-04-18 19:02:08 +00:00 |
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Kip Macsai-Goren
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1ba328324b
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Added GPIO loopback to let outputs cause interrupts
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2022-04-18 07:22:49 +00:00 |
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Kip Macsai-Goren
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64698aa806
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Added working trap test to regression, fixed hanfling of some interrupts
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2022-04-18 07:22:16 +00:00 |
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Shreya Sanghai
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fd3920b217
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replaced k with bpred size
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2022-04-18 04:21:03 +00:00 |
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Shreya Sanghai
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c3164f0ce1
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added bpred size to wally config
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2022-04-18 04:21:03 +00:00 |
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David Harris
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462158ea92
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LSU name cleanup
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2022-04-18 03:18:38 +00:00 |
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Ross Thompson
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a99466a487
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Fixed bug I introduced by csrc cleanup and changes to ILA.
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2022-04-17 21:45:46 -05:00 |
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David Harris
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4a7effaf9e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-04-18 01:30:11 +00:00 |
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David Harris
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2882460c94
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Renamed FinalAMOWriteDataM to AMOWriteDataM
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2022-04-18 01:30:03 +00:00 |
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David Harris
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861fbd698b
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Run 4M instructions in buildroot test to get through kernel & VirtMem startup
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2022-04-18 01:29:38 +00:00 |
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Ross Thompson
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c045e3afd8
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Added back the instret counter to ILA.
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2022-04-17 18:44:07 -05:00 |
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Ross Thompson
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c409bde6ae
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fixed no forcing bug in linux testbench.
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2022-04-17 17:49:51 -05:00 |
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David Harris
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2819a1c305
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Remvoed bytemask anding from FinalWriteDataM in subwordwrite
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2022-04-17 22:33:25 +00:00 |
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David Harris
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812b56acc6
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Prefix comparator cleanup
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2022-04-17 21:53:11 +00:00 |
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David Harris
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de5b61291f
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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Kip Macsai-Goren
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1f9c987efe
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added new tests to makefrag and tests.vh
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2022-04-17 21:00:36 +00:00 |
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Ross Thompson
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059c04e2a8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-17 15:23:46 -05:00 |
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Ross Thompson
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c16dec88de
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Increased uart baud rate to 230400.
Added uart signals to debugger.
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2022-04-17 15:23:39 -05:00 |
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David Harris
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2436534687
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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David Harris
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83d283354c
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Added comments in fcvt
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2022-04-17 16:53:10 +00:00 |
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David Harris
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aa1bac361d
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Simplified SLT logic
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2022-04-17 16:49:51 +00:00 |
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Ross Thompson
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238cc9f9fd
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Commented output power analysis to speed simulation.
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2022-04-16 15:32:59 -05:00 |
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Ross Thompson
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16b3c64234
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-16 14:59:03 -05:00 |
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Ross Thompson
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b9a19304db
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Fixed possible bugs in LRSC.
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2022-04-16 14:45:31 -05:00 |
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David Harris
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68d9c99fba
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Added WFI support to IFU to keep it in the pipeline
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2022-04-14 17:26:17 +00:00 |
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David Harris
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a28831b83e
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Added WFI to the testbench instruction name decoder
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2022-04-14 17:12:11 +00:00 |
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David Harris
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855d68afde
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WFI should set EPC to PC+4
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2022-04-14 17:05:22 +00:00 |
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bbracker
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fe53dd1683
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fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
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2022-04-14 09:23:21 -07:00 |
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bbracker
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eb21e34000
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fix ReadDataM forcing
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2022-04-13 15:32:00 -07:00 |
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Ross Thompson
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2e8afd071e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-13 13:39:47 -05:00 |
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bbracker
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5de92af0b1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-13 05:35:56 -07:00 |
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bbracker
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735c75af55
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change interrupt spoofing to happen at negative clock edges
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2022-04-13 04:31:23 -07:00 |
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bbracker
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52ed99ca1b
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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03f1c01f14
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whoops forgot to update AttemptedInstructionCount in interrupt spoofing
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2022-04-13 00:49:37 -07:00 |
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bbracker
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d3e9703c19
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change testbench-linux to by default use attempted instruction count for warning/error messages
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2022-04-12 21:22:08 -07:00 |
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Ross Thompson
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bb6f1cf816
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-12 19:38:04 -05:00 |
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Ross Thompson
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fc173a7954
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Missed the force on uart for no tracking.
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2022-04-12 19:37:44 -05:00 |
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Ross Thompson
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ff826fdb02
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-12 17:56:48 -05:00 |
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Ross Thompson
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7d0462dc59
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UART and clock speed changes to support 30Mhz.
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2022-04-12 17:56:36 -05:00 |
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