61 Commits

Author	SHA1	Message	Date
Ross Thompson	bbb47fc943	Changed the performance counters to track different data. ... Now rather than tracking jump(r) we track jump(r) and taken branches.	2023-01-26 13:21:28 -06:00
Ross Thompson	07308e2c14	Removed mark_debug from all source code.	2023-01-20 18:47:36 -06:00
David Harris	53d0d28828	csr cleanup	2023-01-13 22:12:06 -08:00
David Harris	97bddf0d54	csr cleanup	2023-01-13 21:09:29 -08:00
David Harris	e4f4b31896	csr cleanup	2023-01-13 21:00:06 -08:00
David Harris	7358402bc0	csr cleanup	2023-01-13 20:55:21 -08:00
David Harris	9da2fae1f3	csr comments	2023-01-13 20:49:34 -08:00
David Harris	370678f730	trap comments	2023-01-13 19:44:38 -08:00
Ross Thompson	8e3e8591a6	Removed 1 bit from instruction classification.	2023-01-13 15:19:53 -06:00
David Harris	7d93659f6b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	b911056e66	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	e92cffbb5e	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	15b829bbf7	Removed unused signals	2023-01-07 06:06:54 -08:00
Ross Thompson	e34f80db2f	More branch predictor cleanup.	2023-01-05 17:19:27 -06:00
Ross Thompson	8ca6c1255e	More branch predictor cleanup.	2023-01-05 13:36:51 -06:00
Ross Thompson	b5a85b55f1	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. ... Generate WFIStallM in the privileged unit rather than generate in hazard. Cleaned up the hazard cause logic to be consistent across all causes.	2022-12-23 15:10:37 -06:00
David Harris	1f6dc62bb3	Moved InstrValidNotFLushed to csr including InstrValidM	2022-12-23 00:27:44 -08:00
David Harris	85d0b697bf	Removed unused StallW from CSRs	2022-12-23 00:21:36 -08:00
David Harris	93bb8036be	Revert to 98b824	2022-12-22 23:58:14 -08:00
David Harris	51b92285d3	Removed unused signals in FPU and CSR	2022-12-22 22:59:05 -08:00
David Harris	ca949f2110	Only delegated bits of SIP are readable	2022-12-21 12:32:49 -08:00
Ross Thompson	f6393d1288	Waiting on fix for wally64periph uart test. ... would like to remove vectored interrupt adder.	2022-12-21 13:16:09 -06:00
Ross Thompson	c41d58bd29	Vectored interrupts now require 64 byte alignment. ... Eliminates adder.	2022-12-21 12:05:49 -06:00
David Harris	28085ce8eb	Clean up vecgtored interrupts	2022-12-20 16:53:09 -08:00
David Harris	88ee834c97	Converted tvecmux to structural	2022-12-20 16:24:04 -08:00
Ross Thompson	2f0d20b8b0	privileged pc mux cleanup.	2022-12-20 18:05:44 -06:00
Ross Thompson	cba2ed64e5	Moved privileged pc logic into privileged unit.	2022-12-20 17:55:45 -06:00
Ross Thompson	ef4ecbe62b	Changed long names of vectored pcm signals.	2022-12-20 17:01:20 -06:00
David Harris	f5e2cff45a	Cause simplification	2022-05-12 23:47:21 +00:00
David Harris	c4621c5b6b	Cause simplification	2022-05-12 23:37:40 +00:00
David Harris	7daf631c13	Cause simplification	2022-05-12 23:33:35 +00:00
David Harris	803bfc4fe4	Cause simplification	2022-05-12 23:29:35 +00:00
David Harris	87dadc8208	trap/csr cleanup	2022-05-12 22:26:21 +00:00
David Harris	2eb6a65fa2	More trap/csr simplification	2022-05-12 22:04:20 +00:00
David Harris	2d8ccbd4ea	More trap/csr simplification	2022-05-12 22:00:23 +00:00
David Harris	417e36bff5	More trap/csr simplification	2022-05-12 21:55:50 +00:00
David Harris	ca6b7716e2	Simplifying trap/csr interface	2022-05-12 21:50:15 +00:00
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	fb725a9e0a	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	66424a8246	SFENCE.VMA should be illegal in user mode	2022-05-05 15:15:02 +00:00
David Harris	c100c9893b	wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts	2022-05-05 14:37:21 +00:00
David Harris	554c2b3550	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
David Harris	9c4de0e9c1	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
David Harris	0ede295e88	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
David Harris	855d68afde	WFI should set EPC to PC+4	2022-04-14 17:05:22 +00:00
David Harris	6966554ee8	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
Ross Thompson	5ef6cde52e	Added more ILA signals.	2022-04-02 16:39:45 -05:00