David Harris
|
8d348dacce
|
Started atomics
|
2021-07-17 21:11:41 -04:00 |
|
David Harris
|
574f7d9c32
|
moved subwordread to lsu
|
2021-07-17 20:37:20 -04:00 |
|
David Harris
|
e82374d19f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-17 20:01:23 -04:00 |
|
David Harris
|
9a86fc899b
|
LSU cleanup
|
2021-07-17 20:01:03 -04:00 |
|
David Harris
|
d9750c16a5
|
Pushing HPTWPAdrM flop into LSUArb
|
2021-07-17 19:39:18 -04:00 |
|
David Harris
|
586341a41a
|
Simplified VPN case statement
|
2021-07-17 19:34:01 -04:00 |
|
Ross Thompson
|
9cfbc4aec0
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-17 18:27:44 -05:00 |
|
David Harris
|
35b7577be2
|
Finished HPTW TranslationPAdr simlification
|
2021-07-17 19:27:24 -04:00 |
|
Ross Thompson
|
1aac97030a
|
Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before.
|
2021-07-17 18:26:29 -05:00 |
|
David Harris
|
2b1fdfbae2
|
Further TranslationVAdr simplification
|
2021-07-17 19:24:37 -04:00 |
|
David Harris
|
b785a20f90
|
Continued Translation Address Cleanup of TranslationPAdrMux
|
2021-07-17 19:16:56 -04:00 |
|
David Harris
|
fc88b3a693
|
Continued Translation Address Cleanup
|
2021-07-17 19:09:13 -04:00 |
|
David Harris
|
6536ef8dce
|
Refining address interface between HPTW and LSU
|
2021-07-17 19:02:18 -04:00 |
|
David Harris
|
7b92e7e590
|
Fixed bad register in I-FSD-01 Imperas test.
|
2021-07-17 17:08:07 -04:00 |
|
David Harris
|
a67292b5f3
|
trap.sv comment cleanup
|
2021-07-17 16:01:07 -04:00 |
|
David Harris
|
c1c3249709
|
trap.sv cleanup
|
2021-07-17 15:57:10 -04:00 |
|
David Harris
|
af5e1f7f39
|
Finished removing PageTableEntry redundant signals from hptw
|
2021-07-17 15:50:52 -04:00 |
|
David Harris
|
e182cac9bc
|
hptw: Removed NonBusTrapM from LSU
|
2021-07-17 15:24:26 -04:00 |
|
David Harris
|
2f81e4c70d
|
hptw: Removed NonBusTrapM from LSU
|
2021-07-17 15:22:24 -04:00 |
|
David Harris
|
863e6e72d6
|
hptw: Propagating PageTableEntryF removal through IFU
|
2021-07-17 15:04:39 -04:00 |
|
David Harris
|
a855e0170e
|
hptw: Propagating PageTableEntryF removal through LSU
|
2021-07-17 15:01:01 -04:00 |
|
David Harris
|
d4eeabe355
|
hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE
|
2021-07-17 14:48:44 -04:00 |
|
David Harris
|
86e04c080d
|
hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states
|
2021-07-17 14:36:27 -04:00 |
|
David Harris
|
714eef4a1a
|
hptw: Eliminated A and D bit faults while walking page table, per spec
|
2021-07-17 14:29:20 -04:00 |
|
David Harris
|
90c5312f85
|
hptw: Simplified TranslationVAdr calculation based just on DTLBWalk
|
2021-07-17 14:16:33 -04:00 |
|
David Harris
|
42aee1db30
|
hptw: renamed DTLBMissQ to DTLBWalk
|
2021-07-17 14:13:00 -04:00 |
|
David Harris
|
6f22e9a393
|
hptw: renamed ADRE to ADR
|
2021-07-17 14:02:59 -04:00 |
|
David Harris
|
3ce22a60b3
|
hptw: replaced PreviousWalkerState with a PageType FSM
|
2021-07-17 13:54:58 -04:00 |
|
David Harris
|
89fd653cc1
|
hptw: removed ITLBMissFQ
|
2021-07-17 13:44:08 -04:00 |
|
David Harris
|
87aa527de7
|
hptw: minor cleanup
|
2021-07-17 13:40:12 -04:00 |
|
David Harris
|
ea2aa469a1
|
hptw: Simplifed out AnyTLBMiss
|
2021-07-17 12:07:51 -04:00 |
|
David Harris
|
784e6cf538
|
hptw: Renamed Memstore to MemWrite
|
2021-07-17 12:01:43 -04:00 |
|
David Harris
|
0a6622a6fb
|
hptw: Merged RV32/64 FSMs
|
2021-07-17 11:55:24 -04:00 |
|
David Harris
|
cf0975c937
|
hptw: FSM simplification
|
2021-07-17 11:41:43 -04:00 |
|
David Harris
|
4469b5a4b3
|
hptw: default state should be unreachable
|
2021-07-17 11:33:16 -04:00 |
|
David Harris
|
9cee6c2281
|
hptw: factored Misaligned
|
2021-07-17 11:31:16 -04:00 |
|
David Harris
|
fa12727bbb
|
hptw: factored HPTWRead
|
2021-07-17 11:25:59 -04:00 |
|
David Harris
|
708f8cc3a2
|
hptw: factored HPTWRead
|
2021-07-17 11:25:52 -04:00 |
|
David Harris
|
ef63e1ab52
|
hptw: factored pregen
|
2021-07-17 11:11:10 -04:00 |
|
David Harris
|
880aa1c03a
|
HPTW: more cleanup
|
2021-07-17 04:55:01 -04:00 |
|
David Harris
|
a0f6c9aec1
|
HPTW: factored out DTLBWrite/ITLBWrite
|
2021-07-17 04:44:23 -04:00 |
|
David Harris
|
08e494dd7d
|
HPTW: factored out PageTableENtry
|
2021-07-17 04:40:01 -04:00 |
|
David Harris
|
bd270acdb6
|
more cleaning up FSM
|
2021-07-17 04:35:51 -04:00 |
|
David Harris
|
6d8a6eeba0
|
cleaning up FSM
|
2021-07-17 04:26:41 -04:00 |
|
David Harris
|
330e500442
|
Simplify FSM
|
2021-07-17 04:12:31 -04:00 |
|
David Harris
|
03ef3f7f17
|
Pulled TranslationPAdr mux out of HPTW FSM
|
2021-07-17 04:06:26 -04:00 |
|
David Harris
|
5698433463
|
Simplified bad PTE detection
|
2021-07-17 03:30:17 -04:00 |
|
David Harris
|
ac67342dd4
|
Pulled out shared PTEReg
|
2021-07-17 03:21:09 -04:00 |
|
David Harris
|
86ca9abe42
|
Flip-flop clean-up
|
2021-07-17 03:15:47 -04:00 |
|
David Harris
|
9a15a2f7df
|
Flip-flop clean-up
|
2021-07-17 03:12:24 -04:00 |
|
David Harris
|
8241dd4599
|
Flip-flop clean-up
|
2021-07-17 03:10:17 -04:00 |
|
David Harris
|
a8a5fa4b3c
|
Started pagetablewalker cleanup: combined state flops shared for both RV versions
|
2021-07-17 02:53:52 -04:00 |
|
David Harris
|
b65788d165
|
Replaced separate PageTypeF and PageTypeM with common PageType
|
2021-07-17 02:31:23 -04:00 |
|
David Harris
|
dac22d5016
|
Removed more unused signals from ahblite
|
2021-07-17 02:21:54 -04:00 |
|
David Harris
|
a898bbb991
|
Removed rest of HRDATAW from ahblite
|
2021-07-17 02:15:24 -04:00 |
|
David Harris
|
a19d3f126f
|
Commented out HRDATAW logic in ebu
|
2021-07-17 02:10:57 -04:00 |
|
David Harris
|
e3dc59c5a2
|
renamed or_rows.sv
|
2021-07-16 20:17:03 -04:00 |
|
Ross Thompson
|
0b3dc288ec
|
Made furture progress in the mmu tests.
|
2021-07-16 15:56:06 -05:00 |
|
Ross Thompson
|
6521d2b468
|
Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
|
2021-07-16 14:21:09 -05:00 |
|
Ross Thompson
|
46bce70e42
|
Fixed walker fault interaction with dcache.
|
2021-07-16 12:22:13 -05:00 |
|
Ross Thompson
|
e0f719d513
|
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
|
2021-07-16 11:12:57 -05:00 |
|
Kip Macsai-Goren
|
abd5b1c02d
|
Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
|
2021-07-15 18:30:29 -04:00 |
|
Ross Thompson
|
e5d624c1fa
|
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
|
2021-07-15 11:56:35 -05:00 |
|
Ross Thompson
|
fa26aec588
|
Merge branch 'main' into dcache
|
2021-07-15 11:55:20 -05:00 |
|
Ross Thompson
|
b9902b0560
|
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
|
2021-07-15 11:00:42 -05:00 |
|
Ross Thompson
|
8610ef204c
|
Renamed DCacheStall to LSUStall in hart and hazard.
Added missing logic in lsu.
|
2021-07-15 10:16:16 -05:00 |
|
Ross Thompson
|
704f4f724e
|
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
|
2021-07-14 23:08:07 -05:00 |
|
Ross Thompson
|
ba1e1ec231
|
Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
|
2021-07-14 22:26:07 -05:00 |
|
Katherine Parry
|
c74d26eea4
|
Fixed lint warning
|
2021-07-14 21:24:48 -04:00 |
|
Ross Thompson
|
c79650b508
|
Added d cache StallW checks for any time the cache wants to go to STATE_READY.
|
2021-07-14 17:25:50 -05:00 |
|
Ross Thompson
|
2c946a282f
|
Fixed d cache not honoring StallW for uncache writes and reads.
|
2021-07-14 17:23:28 -05:00 |
|
Katherine Parry
|
f5bfdf46db
|
fpu unpacking unit created
|
2021-07-14 17:56:49 -04:00 |
|
Ross Thompson
|
e91501985c
|
Routed CommittedM and PendingInterruptM through the lsu arb.
|
2021-07-14 16:18:09 -05:00 |
|
Ross Thompson
|
adce800041
|
Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled.
|
2021-07-14 15:47:38 -05:00 |
|
Ross Thompson
|
d78e31e9df
|
Forgot to include one hot decoder.
|
2021-07-14 15:46:52 -05:00 |
|
Ross Thompson
|
f4295ff097
|
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
|
2021-07-14 15:00:33 -05:00 |
|
James Stine
|
e6d19be87c
|
put back for now to test fdiv
|
2021-07-14 06:48:29 -05:00 |
|
Ross Thompson
|
9b756d6a94
|
Implemented uncached reads.
|
2021-07-13 23:03:09 -05:00 |
|
Ross Thompson
|
e8bf502bc2
|
Added CommitedM to data cache output.
|
2021-07-13 22:43:42 -05:00 |
|
Ross Thompson
|
3e57c899a2
|
Partially working changes to support uncached memory access. Not sure what CommitedM is.
|
2021-07-13 17:24:59 -05:00 |
|
James E. Stine
|
46001fef27
|
mod 2 of fpdivsqrt update
|
2021-07-13 16:59:17 -04:00 |
|
James E. Stine
|
8382a17969
|
Update fpdivsqrt item until move into uarch
|
2021-07-13 16:53:20 -04:00 |
|
Ross Thompson
|
baa2b5d15f
|
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
|
2021-07-13 14:51:42 -05:00 |
|
Ross Thompson
|
3c1a717399
|
Fixed the fetch buffer accidental overwrite on eviction.
|
2021-07-13 14:21:29 -05:00 |
|
Ross Thompson
|
32f27cfecf
|
Dcache AHB address generation was wrong. Needed to zero the offset.
|
2021-07-13 14:19:04 -05:00 |
|
Ross Thompson
|
afc1bc9c38
|
Moved StoreStall into the hazard unit instead of in the d cache.
|
2021-07-13 13:20:50 -05:00 |
|
David Harris
|
9de97c1e20
|
Fixed busybear by restoring InstrValidW needed by testbench
|
2021-07-13 14:17:36 -04:00 |
|
Ross Thompson
|
47e16f5629
|
Fixed back to back store issue.
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
|
2021-07-13 12:46:20 -05:00 |
|
David Harris
|
2ba82d1a5c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-13 13:26:51 -04:00 |
|
David Harris
|
223086ac33
|
added or.sv
|
2021-07-13 13:26:40 -04:00 |
|
Katherine Parry
|
ca19b2e215
|
Fixed writting MStatus FS bits
|
2021-07-13 13:22:04 -04:00 |
|
Katherine Parry
|
efdec72df1
|
Fixed writting MStatus FS bits
|
2021-07-13 13:20:30 -04:00 |
|
David Harris
|
b5dddec858
|
Fixed InstrValid from W to M stage for CSR performance counters
|
2021-07-13 13:19:13 -04:00 |
|
Ross Thompson
|
224e3b2991
|
Fixed subword write. subword read should not feed into subword write.
|
2021-07-13 11:21:44 -05:00 |
|
David Harris
|
861ef5e1cb
|
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
|
2021-07-13 09:32:02 -04:00 |
|
Ross Thompson
|
49f6eec579
|
Team work on solving the dcache data inconsistency problem.
|
2021-07-12 23:46:32 -05:00 |
|
Ross Thompson
|
1cc258ade1
|
Progress towards the test bench flush.
|
2021-07-12 14:22:13 -05:00 |
|
Katherine Parry
|
f3ac46df86
|
fcvt.sv cleanup
|
2021-07-11 21:30:01 -04:00 |
|
Katherine Parry
|
36f59f3c99
|
Almost all convert instructions pass Imperas tests
|
2021-07-11 18:06:33 -04:00 |
|
Ross Thompson
|
f26d635614
|
Fixed the spurious AHB requests to address 0. Somehow by not having a default
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
|
2021-07-10 22:34:47 -05:00 |
|