Ross Thompson
3dd89a7e62
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 10:38:24 -05:00
Ross Thompson
25a8920a69
Tested all numbers of ways for dcache 1, 2, 4, and 8.
2021-07-22 10:38:07 -05:00
bbracker
d3059dd04c
fix UART RX FIFO bug where tail pointer can overtake head pointer
2021-07-22 02:09:41 -04:00
Ross Thompson
dac93bb366
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
c69a5dc8a6
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
71375ba655
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:39:07 -05:00
Ross Thompson
7785401281
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 14:56:30 -05:00
Ross Thompson
313bc5255c
Improved address bus names and usages in the walker, dcache, and tlbs.
...
Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
310b454fa1
Added comment about better muxing.
2021-07-21 14:40:14 -05:00
Ross Thompson
5860f147d4
4 way set associative is now working.
2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
4eaf95de60
Fixed TLB parameterization and valid bit flop to correctly do instr page faults
2021-07-21 14:44:43 -04:00
Katherine Parry
01f0b4e5df
FDIV and FSQRT work
2021-07-21 14:08:14 -04:00
Ross Thompson
e0990535e1
Fixed remaining bugs in 2 way set associative dcache.
2021-07-21 10:35:23 -05:00
Ross Thompson
3f780f012a
Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux.
...
Also forgot to include cacheLRU.sv file.
2021-07-20 23:17:42 -05:00
Katherine Parry
b9081e514c
FMA parameterized
2021-07-20 22:04:21 -04:00
Ross Thompson
14e949d6e3
Partially working 2 way set associative d cache.
2021-07-20 17:51:42 -05:00
bbracker
f9b6bd91f5
fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
2021-07-20 17:55:44 -04:00
David Harris
e5e3f5abe6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 14:46:58 -04:00
David Harris
1f3dfa20f6
flag for optional boottim
2021-07-20 14:46:37 -04:00
Ross Thompson
00081ebc68
Replaced FinalReadDataM with ReadDataM in dcache.
2021-07-20 13:27:29 -05:00
David Harris
e1a1a8395e
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
James E. Stine
12e09a7ace
slight mod to fpdiv - still bug in batch vs. non-batch
2021-07-20 01:47:46 -04:00
Ross Thompson
365485bd8b
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
David Harris
23b76a724d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 18:19:59 -04:00
Kip Macsai-Goren
5880cbafe4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 16:46:46 -04:00
bbracker
bc5222e721
put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
2021-07-19 16:19:24 -04:00
bbracker
64e0fe4c5a
whoops MTIMECMP is always 64 bits
2021-07-19 15:40:53 -04:00
bbracker
bdb1ece183
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:13:14 -04:00
bbracker
cd469035be
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
Kip Macsai-Goren
2614df627e
added changes to priority encoders from synthesis branch (correctly this time I hope)
2021-07-19 15:06:14 -04:00
Ross Thompson
bf3ca50a9a
Furture simplification of the dcache ReadDataW update.
2021-07-19 12:46:31 -05:00
Ross Thompson
b61dad4b83
Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
2021-07-19 12:32:16 -05:00
Ross Thompson
4d53b9002f
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
bbracker
67eb1f5c6b
change sram1rw to have a small delay so that we don't have signals changing on clock edges
2021-07-19 11:30:07 -04:00
David Harris
2ed6285a3d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 10:34:18 -04:00
James Stine
7d571f27a6
delete sbtm_a4 and sbtm_a5 as they are not needed
2021-07-19 08:06:00 -05:00
James Stine
186b5dee69
remove sbtm3.sv - not needed
2021-07-19 08:00:53 -05:00
James Stine
5b1f9797f5
update part I on sbtm change
2021-07-19 07:59:27 -05:00
David Harris
8e01007d1c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 00:25:06 -04:00
Katherine Parry
c9180f4ebd
FDIV and FSQRT passes when simulating in modelsim
2021-07-18 23:00:04 -04:00
David Harris
46ab609498
Updated FMA1 with parameterized size
2021-07-18 20:40:49 -04:00
David Harris
ed64d37e65
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-18 17:36:29 -04:00
David Harris
4f8f52f283
Added FLEN, NE, NF to config and started using these in FMA1
2021-07-18 17:28:25 -04:00
Katherine Parry
60dabb9094
fdivsqrt inegrated, but not completley working
2021-07-18 14:03:37 -04:00
David Harris
8317be5aed
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
David Harris
c75d70126f
LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall
2021-07-18 03:51:30 -04:00
David Harris
3f7a3b280e
HPTW: Simpliifieid PRegEn
2021-07-18 03:35:38 -04:00
David Harris
60bd27a40e
Removed EndWalk signal and simplified TLBMissReg
2021-07-18 03:26:43 -04:00
Ross Thompson
009c5314b4
Fixed LRSC in 64bit version. 32bit version is broken.
2021-07-17 20:58:49 -05:00
David Harris
8bdf1eaf0f
added lrsc.sv
2021-07-17 21:15:08 -04:00
