Fixed InstrValid from W to M stage for CSR performance counters

wally-pipelined/src/ieu/controller.sv

@@ -60,7 +60,6 @@ module controller(
   input  logic       StallW, FlushW,
   output logic 	     RegWriteW,     // for datapath and Hazard Unit
   output logic [2:0] ResultSrcW,
-  output logic       InstrValidW,
   // Stall during CSRs
   output logic       CSRWritePendingDEM
 );
@@ -214,9 +213,9 @@ module controller(
                          {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, AtomicM, InstrValidM});
   
   // Writeback stage pipeline control register
-  flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
-                         {RegWriteM, ResultSrcM, InstrValidM},
-                         {RegWriteW, ResultSrcW, InstrValidW});  
+  flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW,
+                         {RegWriteM, ResultSrcM},
+                         {RegWriteW, ResultSrcW});  
 
   assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM;   
 endmodule

wally-pipelined/src/ieu/ieu.sv

@@ -60,7 +60,7 @@ module ieu (
   input logic [`XLEN-1:0]  CSRReadValW, ReadDataW, MulDivResultW,
   input logic 		   FWriteIntW,
   // input  logic [`XLEN-1:0] PCLinkW,
-  output logic 		   InstrValidM, InstrValidW,
+  output logic 		   InstrValidM,
   // hazards
   input logic 		   StallD, StallE, StallM, StallW,
   input logic 		   FlushD, FlushE, FlushM, FlushW,

wally-pipelined/src/privileged/csr.sv

@@ -40,7 +40,7 @@ module csr #(parameter
   input  logic             CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
   input  logic             TimerIntM, ExtIntM, SwIntM,
   input  logic [63:0]      MTIME_CLINT, MTIMECMP_CLINT,
-  input  logic             InstrValidW, FloatRegWriteW, LoadStallD,
+  input  logic             InstrValidM, FloatRegWriteW, LoadStallD,
   input  logic 		   BPPredDirWrongM,
   input  logic 		   BTBPredPCWrongM,
   input  logic 		   RASPredPCWrongM,

wally-pipelined/src/privileged/csrc.sv

@@ -72,7 +72,7 @@ module csrc #(parameter
 ) (
     input  logic             clk, reset,
     input  logic             StallD, StallE, StallM, StallW,
-    input  logic             InstrValidW, LoadStallD, CSRMWriteM,
+    input  logic             InstrValidM, LoadStallD, CSRMWriteM,
     input  logic             BPPredDirWrongM,
     input  logic             BTBPredPCWrongM,
     input  logic             RASPredPCWrongM,
@@ -114,7 +114,7 @@ module csrc #(parameter
       // Counter adders with inhibits for power savings
       assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]};
       //assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
-      assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~StallW & ~MCOUNTINHIBIT_REGW[2]};
+      assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidM & ~StallW & ~MCOUNTINHIBIT_REGW[2]};
       //assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls
       //assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
       assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];
@@ -134,7 +134,7 @@ module csrc #(parameter
         // could replace special counters 0-2 with this loop for all counters
         assign CounterEvent[0] = 1'b1;
         assign CounterEvent[1] = 1'b0;
-        assign CounterEvent[2] = InstrValidW & ~StallW;
+        assign CounterEvent[2] = InstrValidM & ~StallW;
         assign CounterEvent[3] = LoadStallD & ~StallD;
         assign CounterEvent[4] = BPPredDirWrongM & ~StallM;
         assign CounterEvent[5] = InstrClassM[0] & ~StallM;
@@ -339,7 +339,7 @@ module csrc #(parameter
   HPMCOUNTERHBASE = 12'hC80,
   )(input logic 	     clk, reset,
     input logic 	     StallD, StallE, StallM, StallW,
-    input logic 	     InstrValidW, LoadStallD, CSRMWriteM,
+    input logic 	     InstrValidM, LoadStallD, CSRMWriteM,
     input logic 	     BPPredDirWrongM,
     input logic 	     BTBPredPCWrongM,
     input logic 	     RASPredPCWrongM,
@@ -381,7 +381,7 @@ module csrc #(parameter
     logic [`COUNTERS:0] MCOUNTEN;
     assign MCOUNTEN[0] = 1'b1;
     assign MCOUNTEN[1] = 1'b0;
-    assign MCOUNTEN[2] = InstrValidW & ~StallW;
+    assign MCOUNTEN[2] = InstrValidM & ~StallW;
     assign MCOUNTEN[3] = LoadStallD & ~StallD;
     assign MCOUNTEN[4] = BPPredDirWrongM & ~StallM;
     assign MCOUNTEN[5] = InstrClassM[0] & ~StallM;

wally-pipelined/src/privileged/privileged.sv

@@ -38,7 +38,7 @@ module privileged (
   output logic [`XLEN-1:0] PrivilegedNextPCM,
   output logic             RetM, TrapM, NonBusTrapM,
   output logic             ITLBFlushF, DTLBFlushM,
-  input  logic             InstrValidM,InstrValidW, CommittedM,
+  input  logic             InstrValidM, CommittedM,
   input  logic             FloatRegWriteW, LoadStallD,
   input  logic 		   BPPredDirWrongM,
   input  logic 		   BTBPredPCWrongM,

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -74,7 +74,7 @@ module wallypipelinedhart
   logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
   logic [`XLEN-1:0] 	    PrivilegedNextPCM;
   logic [1:0] 		    MemRWM;
-  logic 		    InstrValidM, InstrValidW;
+  logic 		    InstrValidM;
   logic 		    InstrMisalignedFaultM;
   logic 		    DataMisalignedM;
   logic 		    IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;