88 Commits

Author	SHA1	Message	Date
Ross Thompson	3dbf6790e1	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
Ross Thompson	11e5aad38a	Moved subcachelineread inside the cache. There is some ugliness to still resolve.	2022-03-11 12:44:04 -06:00
Ross Thompson	a12016e69b	Moved subcacheline read inside the cache.	2022-03-11 11:03:36 -06:00
Ross Thompson	326ecda060	removed unused parameter.	2022-03-11 10:43:54 -06:00
Ross Thompson	04dd2f0eb5	atomic cleanup.	2022-03-10 18:56:37 -06:00
Ross Thompson	a598760445	Name changes.	2022-03-10 18:50:03 -06:00
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	50789f9ddd	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
Ross Thompson	f7df3a0666	Progress on the path to getting all configs working with byte write enables.	2022-03-10 17:02:52 -06:00
Ross Thompson	83133f8c47	Partially working byte write enables. Works for cache, but not dtim or bus only.	2022-03-10 16:11:39 -06:00
Ross Thompson	d5f524a15e	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
Ross Thompson	ed32801cc1	Comments.	2022-03-08 18:05:25 -06:00
Ross Thompson	acd60218b8	Removed unused signal.	2022-03-08 16:58:26 -06:00
Ross Thompson	60e6c1ffa7	Moved cacheable signal into cache.	2022-03-08 16:34:02 -06:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
Ross Thompson	6a52f95cc8	Minor busdp cleanup.	2022-02-22 17:28:26 -06:00
Ross Thompson	56fc6d0d7c	Minor cleanup of lsu.	2022-02-21 12:46:06 -06:00
Ross Thompson	f48b12b089	Moved mux into lsuvirtmem.	2022-02-21 09:31:29 -06:00
Ross Thompson	ae06785b9f	Minor changes to LSU.	2022-02-19 14:38:17 -06:00
Ross Thompson	0eec096474	Rough implementation passing regression test with hptw atomic writes to memory.	2022-02-17 14:46:11 -06:00
Ross Thompson	62f5f1e622	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	c9e33208e3	Moved a few muxes around after sww changes.	2022-02-16 15:43:03 -06:00
Ross Thompson	71ed49bf2b	cleanup of signal names.	2022-02-16 15:29:08 -06:00
Ross Thompson	27042f028e	Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.	2022-02-16 15:22:19 -06:00
Ross Thompson	1e7e59bdbd	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
Ross Thompson	c8e6884926	Fixed bug. ... It was possible for DTLBMissM to prevent a dcache flush.	2022-02-11 14:00:01 -06:00
Ross Thompson	411997010b	Replacement policy cleanup.	2022-02-10 11:40:10 -06:00
Ross Thompson	382d5fab0f	Cleanup.	2022-02-10 11:27:15 -06:00
Ross Thompson	3a0af5d9e9	Cleanup + critical path optimizations.	2022-02-10 11:11:16 -06:00
Ross Thompson	911ee36b22	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
Ross Thompson	3cd067ac6a	Finished merge.	2022-02-08 11:36:24 -06:00
Ross Thompson	1766c0f5ba	Removed unused ports from caches and buses.	2022-02-04 22:52:51 -06:00
Ross Thompson	dce4f8a0e5	Cleanup.	2022-02-04 22:40:51 -06:00
Ross Thompson	53551ab533	Moved the hwdata mux back into the busdp.	2022-02-04 22:39:13 -06:00
Ross Thompson	34cf77797a	Merged together the two sub cache line read muxes. ... One mux was used for loads and the other for eviction.	2022-02-04 22:30:04 -06:00
Ross Thompson	c846368537	Moved the sub cache line read logic to lsu/ifu.	2022-02-04 20:42:53 -06:00
David Harris	e92461159d	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	9e0055cbb9	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
Ross Thompson	b05abc1795	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	d2ab17e1af	Repaired linux-wave.do	2022-01-31 12:54:18 -06:00
Ross Thompson	fa8914a830	Cleanup busdp.	2022-01-31 12:17:07 -06:00
Ross Thompson	7c3d6bbdb4	Moved lsu virtual memory logic into separate module.	2022-01-31 11:56:03 -06:00
Ross Thompson	e35a8299ec	Encapsulated dtim.	2022-01-31 11:23:55 -06:00
Ross Thompson	dbe40856a2	Removed unused signals in the LSU.	2022-01-31 10:35:35 -06:00
Ross Thompson	bfbc31d184	Moved atomic logic to own module.	2022-01-31 10:28:12 -06:00
Ross Thompson	ef770fd183	Encapsulated the bus data path into a separate module.	2022-01-31 10:15:48 -06:00
Ross Thompson	d52c5b0393	LSU and IFU cleanup.	2022-01-28 15:26:06 -06:00
Ross Thompson	147d71fd46	Clean up of mmu instances in IFU and LSU.	2022-01-28 14:02:05 -06:00