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398 Commits

Author SHA1 Message Date
Thomas Fleming
38a0199260 Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Noah Boorstin
75f58c4df5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
118e846ef7 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
43532be770 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Ross Thompson
a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
0994d03b28 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
f7cbaeb217 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
6619a5f44f Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
2a308309e4 fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
6e83ccc3c4 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
108f18e580 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
8723fb916c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
637bba6509 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
b5a1691c2b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
cc988f420f removed minor bugs 2021-03-25 20:29:50 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
3b4f0141f4 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
44060b579b busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Domenico Ottolia
f134b09a97 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
682050a33b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
Teo Ene
a3aa103dc7 Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
e43849b82c Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Ross Thompson
11109e5a88 Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
d67e28bf50 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Ross Thompson
5edc90b1c2 added a whole bunch of interseting test code for branches which does not work. 2021-03-23 13:54:59 -05:00
Ross Thompson
9e61481414 Added first benchmark. 2021-03-23 13:54:59 -05:00
Ross Thompson
e1842c8da6 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
Noah Boorstin
69e5319675 busybear: more progress 2021-03-23 14:49:30 -04:00
Noah Boorstin
24e403bc35 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
f3194c6388 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Noah Boorstin
d5bd5fa9d7 start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
15474f678d Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
849641f31e busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
2aa76b27e1 busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
3f897bbf53 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
74bcd9b994 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
5b1db9b6a2 Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
097e8edb3d Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
a2bf5ac202 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
279c09b27c Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
09faa40eb6 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Teo Ene
57f1ca5259 Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
d2fe42d6d0 adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e69376c823 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
4fd0ecff69 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
3e849f99a6 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
dfe6df2e00 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
041439c008 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
da758e9e14 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
3618a39087 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
9f8f0242ca Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Noah Boorstin
bfa7aedd35 busybear: add seperate message on bad memory access becasue its confusing 2021-03-16 21:42:26 -04:00
Domenico Ottolia
d354cbd37d Add privileged testbench 2021-03-16 20:28:38 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
36452749d7 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
400791163e copy Ross's branch predictor preload change into busybear 2021-03-15 18:27:27 -04:00
Ross Thompson
4c8952de6a Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Ross Thompson
7ceef2b0c6 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
David Harris
56b690ccb9 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
865c103599 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
318b642359 Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
a8b242a6ef busybear: account for CSR moving 2021-03-11 06:45:14 +00:00
Jarred Allen
4757794887 Return testbench to normal 2021-03-10 22:58:41 -05:00
Ross Thompson
845115302e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
f92f766573 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
dcae90e3ad I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00
Ross Thompson
50a92247b3 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
Jarred Allen
ae9bcc174d Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
3172be3039 More progress 2021-03-09 21:16:07 -05:00
David Harris
c2f340681d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-09 09:28:32 -05:00
David Harris
17c0f9629a WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Noah Boorstin
4a8b689f62 busybear: better NOPing out of float instructions 2021-03-08 21:24:19 +00:00
Noah Boorstin
c780a25f92 busybear: better instrF checking 
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
 2021-03-08 19:48:12 +00:00
Noah Boorstin
93c9c57426 busybear: load mem files from verilog instead of .do 2021-03-08 19:26:26 +00:00
Noah Boorstin
86142e764a Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
1a11b60664 busybear: slight testbench update 2021-03-05 19:00:40 +00:00
Ross Thompson
264480f258 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Jarred Allen
41f682f848 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Noah Boorstin
dfae278ffb busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Jarred Allen
106718b196 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Noah Boorstin
827dfd774b Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
bbracker
448cba2a5b JALR testing 2021-03-04 10:37:30 -05:00
Teo Ene
06be82fc67 Added stop to coremark_bare testbench 2021-03-04 07:47:07 -06:00
Teo Ene
396dc61564 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00
Teo Ene
6ebb79abe0 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00
Teo Ene
6031269de8 Implemented fix disucssed with Elizabeth 2021-03-03 18:17:53 -06:00
Teo Ene
4562c61af3 Fix to last push 2021-03-03 15:20:38 -06:00
Noah Boorstin
62b441f3f5 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
965d48afe7 busybear: only check pc when it actually changes 2021-03-01 19:08:35 +00:00
Noah Boorstin
4833b36535 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
David Harris
2543c29839 Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Noah Boorstin
bcc0010498 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
db86d20d11 busybear: check instead of providing InstrF 2021-02-28 16:46:53 +00:00
Noah Boorstin
e5e345d161 busybear: instantiate normal wallypipelinedsoc 2021-02-28 06:02:21 +00:00
Ross Thompson
7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
cf03afa880 Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
kaveh pezeshki
c7863d58cd merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
Noah Boorstin
ab9247d625 busybear: add main ram loading, better instr checking also 2021-02-26 20:26:54 +00:00
kaveh Pezeshki
ad631ec3a1 fixed sensitivity list on error checking always block, removed useless once and for all 2021-02-26 13:41:16 -05:00
kaveh pezeshki
d32421822c restored 2021-02-26 02:22:08 -08:00
David Harris
d00d42cf9a Merged bus into main 2021-02-25 00:28:41 -05:00
Teo Ene
3e5de35fc4 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
kaveh pezeshki
3bb8e0d918 condensed always blocks to avoid race conditions 2021-02-24 11:35:28 -08:00
Noah Boorstin
3d82ceffb7 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
 2021-02-24 18:46:09 +00:00
David Harris
f5e9c91193 All tests passing with bus interface 2021-02-24 07:25:03 -05:00
kaveh pezeshki
b36a5614b4 added comments for RAM and bootram, removed trailing whitepace 2021-02-23 21:28:33 -08:00
Noah Boorstin
c8e9edcc43 busybear: add bootram section in the same manner as ram 2021-02-24 02:02:28 +00:00
Noah Boorstin
a24270c4ca busybear: add support for subwords in ram 
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
 2021-02-24 01:51:18 +00:00
Noah Boorstin
00605864fc busybear: start adding ram 2021-02-23 22:01:23 +00:00
Noah Boorstin
d5e7a8a4cf busybear: remove unused signals 2021-02-23 19:38:19 +00:00
Noah Boorstin
ceb7df3561 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
c52a99ce2d Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
817f81c356 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
62d9185212 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
David Harris
cb0054b524 Multiply instructions working 2021-02-17 15:29:20 -05:00
Noah Boorstin
5835641c6c busybear testbench: check (almost) all the CSRs 2021-02-16 20:03:24 -05:00
David Harris
8dec69c2ce Added MUL 2021-02-15 22:27:35 -05:00
Domenico Ottolia
75d9091fe8 Add privileged test cases 2021-02-14 17:01:46 -05:00
Shreya Sanghai
30bfd7534c added branch tests 2021-02-12 22:40:08 -05:00
Noah Boorstin
7312da1a99 busybear: allow testbench to ignore lack of MMU for now 
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing

If it is, we're at 1M instructions!
 2021-02-12 20:08:56 +00:00
Noah Boorstin
97302dd12f busybear: slightly neater error handling 2021-02-12 17:21:56 +00:00
bbracker
9231646fb3 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
Noah Boorstin
5bf6add635 bump into virtual/physcial memory? 2021-02-11 23:06:12 -05:00
Noah Boorstin
4427780a41 busybear: more updates 
now gets to instruction 839037 before failing
also updates to match new gdb output format

umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
 2021-02-11 22:42:58 -05:00
Tejus Rao
5158ca4220 added test cases for ADDW, SUBW, SLLW, SRLW, SRAW 2021-02-11 13:38:38 -05:00
Teo Ene
8a6de4fb86 Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts 2021-02-10 20:48:39 -06:00
ethan-falicov
9edc4b6bfe Fixed merge conflict stuff 2021-02-10 10:03:30 -05:00
ethan-falicov
7e8a58de1a More merge conflicts yay 2021-02-10 09:54:30 -05:00
ethan-falicov
f778f464b7 Merge conflict fixing 2021-02-10 09:45:47 -05:00
ethan-falicov
06541260e0 Adding I Type test cases from Lab 1 2021-02-10 09:39:43 -05:00
David Harris
183a2dcfb5 Debugging bus interface. 2021-02-10 01:43:54 -05:00
David Harris
2357f5513b Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
Jarred Allen
403a0d033c Fix compile error in imperas testbench 2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
81a1eb9a74 merge conflict? 2021-02-07 02:34:49 -05:00
Noah Boorstin
01c0f9db63 Busybear: next week of updates 
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
 - parsed first 1M instructions, and now parse from split GDB runs
 - now at about 230k instructions, can't progress further for now since atomic instructions
   aren't implemented yet
 2021-02-07 03:14:48 +00:00
Jarred Allen
48ade25577 Actually run the WALLY-LOAD tests 2021-02-06 14:56:40 -05:00
bbracker
691d651fde JAL testing 2021-02-05 08:08:42 -05:00
Thomas Fleming
8588a1ed6b Complete STORE tests 2021-02-04 15:38:22 -05:00
Noah Boorstin
dc881bd51b busybear: add more CSRs 2021-02-04 20:13:36 +00:00
Noah Boorstin
d9431d5bed busybear: check initial values also 2021-02-04 19:22:09 +00:00
Noah Boorstin
8d53e36bbc Busybear: start checking CSRs 
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)

and 3 of the CSRs referenced are skipped because of weird locations for them

oh and this doesn't check their initial state, just their changing. This could be a problem
 2021-02-02 06:06:03 +00:00
Noah Boorstin
c634b2f81e busybear: start adding CSR checking 
@kaveh is there a less verbose way to do this?
 2021-02-01 22:08:51 -05:00
Noah Boorstin
ff88214730 busybear: change register file checking to only store register changed 
this should make parsedRegs.txt much smaller
 2021-02-02 01:27:43 +00:00
Noah Boorstin
416b3fc96c Add PCW checking 
for now, doesn't check InstrW because it fails on compressed instructions
 2021-02-01 23:57:33 +00:00
Noah Boorstin
a432d607ce busybear: print warning when NOPing out instructions 2021-02-01 19:44:56 +00:00
Noah Boorstin
b7f63c1dc7 busybear: NOP out floating point instructions for now 
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
 2021-01-30 19:52:47 +00:00
Noah Boorstin
4358f086be update busybear testbench to conform to new structure 
aaaaaaaaaaaaaaaaaahhhh so many changes

also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
 2021-01-30 19:19:00 +00:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
9c81278f28 Added HCLK and HRESETn 2021-01-30 00:56:12 -05:00
David Harris
a357f2a0e7 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
8d4f5277d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 15:38:01 -05:00
David Harris
dc2443c55b Moving data memory to uncore 2021-01-29 15:37:51 -05:00
Noah Boorstin
194d5b55ab update busybear testbench to conform to new structure 2021-01-29 17:46:50 +00:00
David Harris
a94c09cad8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 01:07:22 -05:00
David Harris
ed3cb83c10 Added ahblite bus interface unit 2021-01-29 01:07:17 -05:00
Noah Boorstin
8ab5879af5 busybear testbench: test on first 100k instrs 
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
 2021-01-29 00:14:23 -05:00
Noah Boorstin
619dec1490 busybear: simulate first 10k instructions 
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
 2021-01-28 19:44:58 -05:00
Noah Boorstin
4f84bd3c8f busybear: fix misaligned writing checking 2021-01-28 19:35:09 -05:00
Noah Boorstin
beb93e2508 busybear: add more test instructions 
currently testing first 1k instrs
 2021-01-28 16:41:37 -05:00
Noah Boorstin
287cf4e5a6 oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench 2021-01-28 16:35:12 -05:00
Noah Boorstin
405c9d90b5 busybear testbench: understand bytemask for writes 2021-01-28 15:42:47 -05:00
Noah Boorstin
a4bac85ece busybear: ret is only 1 word 2021-01-28 14:47:40 -05:00
Noah Boorstin
0befdfacec add speculative exception for compressed instructions 2021-01-28 14:40:35 -05:00
Noah Boorstin
27142f0fef testbench now understands lw not aligned to 8 bytes 
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
 2021-01-28 13:33:22 -05:00
Noah Boorstin
a2598b2b30 busybear testbench: check for read data address also 
and check for more end of files better
 2021-01-28 13:16:38 -05:00
Noah Boorstin
f2aea55def update busybear testbench to conform to new structure 2021-01-28 01:21:47 -05:00
Noah Boorstin
28fabb94ee update busybear testbench to conform to new structure 2021-01-27 23:42:19 -05:00
David Harris
4df461ad77 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 22:49:55 -05:00
David Harris
824014c5c0 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
Noah Boorstin
c9baa70e26 update busybear testbench to conform to new structure 2021-01-27 12:54:09 -05:00
David Harris
616afaba69 Moved privileged unit from datapath to hart 2021-01-27 07:46:52 -05:00
David Harris
e84fbd0a73 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 06:40:39 -05:00
David Harris
b88508ca11 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
Noah Boorstin
1195ebb468 show instruction assembly in waveform 2021-01-26 12:34:12 -05:00
Noah Boorstin
6c567aab9a Update busybear tests to conform to new directory structure 2021-01-25 20:37:18 -05:00
Noah Boorstin
e92db93939 Fixed mem write checking 
now passes around 50 instructions!
 2021-01-25 20:07:08 -05:00
Noah Boorstin
358393a1da fix speculation ignoring for PC fetching 2021-01-25 20:07:06 -05:00
David Harris
fa18052348 Added test configurations 2021-01-25 11:28:43 -05:00