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https://github.com/openhwgroup/cvw
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Fix to last push
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37bf3d836f
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@ -32,7 +32,6 @@ module testbench();
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logic [`XLEN-1:0] signature[0:10000];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests[];
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logic [`AHBW-1:0] HRDATAEXT;
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@ -62,9 +61,10 @@ module testbench();
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wallypipelinedsoc dut(.*);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrF,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrDName, InstrEName, InstrMName, InstrWName);
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dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// initialize tests
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initial
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begin
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@ -86,13 +86,13 @@ endmodule
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/* verilator lint_on WIDTH */
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module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrD,
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input logic [31:0] InstrF, InstrD,
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input logic [31:0] InstrE, InstrM,
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output logic [31:0] InstrW,
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output string InstrDName, InstrEName, InstrMName, InstrWName);
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input logic [31:0] InstrW,
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output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB fdec(InstrF, InstrFName);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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