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Linux CoreMark is operational

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This commit is contained in:
Teo Ene 2021-03-04 05:58:18 -06:00
parent 08a7f6ec25
commit 6ebb79abe0
3 changed files with 8 additions and 8 deletions
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6
wally-pipelined/config/coremark/wally-config.vh
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@ -56,7 +56,7 @@
`define MEM_VIRTMEM 0
// Address space
`define RESET_VECTOR 64'h0000000080000000
`define RESET_VECTOR 64'h00000000000100b0
// Bus Interface width
`define AHBW 64
@ -65,8 +65,8 @@
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define TIMBASE 32'h80000000
`define TIMRANGE 32'h00007FFF
`define TIMBASE 32'h00000000
`define TIMRANGE 32'hFFFFFFFF
`define CLINTBASE 32'h02000000
`define CLINTRANGE 32'h0000FFFF
`define GPIOBASE 32'h10012000

6
wally-pipelined/regression/wally-coremark.do
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@ -93,7 +93,7 @@ add wave -divider RAM
add wave -hex -r /testbench/dut/uncore/dtim/RAM
add wave -divider Misc
add wave -divider
add wave -hex -r /testbench/*
#add wave -hex -r /testbench/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
@ -110,6 +110,6 @@ set DefaultRadix hexadecimal
-- Run the Simulation
#run 7402000
run 2780
#run -all
#run 10500
run -all
#quit

4
wally-pipelined/testbench/testbench-coremark.sv
View File

@ -48,7 +48,7 @@ module testbench();
// pick tests based on modes supported
initial
tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"};
tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.elf.memfile", "1000"};
string signame, memfilename;
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
logic UARTSin, UARTSout;
@ -74,7 +74,7 @@ module testbench();
memfilename = tests[0];
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=1911; j < 65535; j = j+1)
for(j=18710; j < 65535; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0;
reset = 1; # 22; reset = 0;
end