mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
845115302e
@ -27,8 +27,8 @@
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
//`define MISA (32'h00000104)
|
||||
`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12)
|
||||
//`define MISA (32'h00000105)
|
||||
`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
|
||||
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
|
||||
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
vsim -c <<!
|
||||
do wally-busybear.do
|
||||
do wally-busybear-batch.do
|
||||
!
|
||||
|
||||
46
wally-pipelined/regression/wally-busybear-batch.do
Normal file
46
wally-pipelined/regression/wally-busybear-batch.do
Normal file
@ -0,0 +1,46 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with testbench_busybear
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work-busybear] {
|
||||
vdel -all -lib work-busybear
|
||||
}
|
||||
vlib work-busybear
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
|
||||
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt +acc=+/testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory +acc=+/testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory work.testbench_busybear -o workopt
|
||||
|
||||
vsim workopt -suppress 8852,12070
|
||||
# load the branch predictors with known data. The value of the data is not important for function, but
|
||||
# is important for perventing pessimistic x propagation.
|
||||
mem load -infile twoBitPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory
|
||||
switch $argc {
|
||||
0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
|
||||
1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
|
||||
}
|
||||
|
||||
run -all
|
||||
quit
|
||||
@ -1,37 +1,37 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with testbench_busybear
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work-busybear] {
|
||||
vdel -all -lib work-busybear
|
||||
}
|
||||
vlib work-busybear
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with testbench_busybear
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work-busybear] {
|
||||
vdel -all -lib work-busybear
|
||||
}
|
||||
vlib work-busybear
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
|
||||
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt +acc work.testbench_busybear -o workopt
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt +acc work.testbench_busybear -o workopt
|
||||
|
||||
vsim workopt -suppress 8852,12070
|
||||
# load the branch predictors with known data. The value of the data is not important for function, but
|
||||
@ -42,40 +42,33 @@ switch $argc {
|
||||
1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
|
||||
}
|
||||
|
||||
mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/bootdtim/RAM
|
||||
mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM
|
||||
mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram
|
||||
mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram
|
||||
mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/dtim/RAM
|
||||
mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/uncore/dtim/RAM
|
||||
mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/RAM
|
||||
mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/imem/RAM
|
||||
|
||||
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave /testbench_busybear/clk
|
||||
add wave /testbench_busybear/reset
|
||||
add wave -divider
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave /testbench_busybear/clk
|
||||
add wave /testbench_busybear/reset
|
||||
add wave -divider
|
||||
add wave -hex /testbench_busybear/PCtext
|
||||
add wave -hex /testbench_busybear/pcExpected
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCF
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/InstrF
|
||||
add wave -hex /testbench_busybear/dut/InstrF
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCF
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/InstrF
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/StallD
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
|
||||
add wave /testbench_busybear/CheckInstrF
|
||||
add wave /testbench_busybear/lastCheckInstrF
|
||||
add wave /testbench_busybear/speculative
|
||||
add wave /testbench_busybear/lastPC2
|
||||
add wave -divider
|
||||
add wave -divider
|
||||
add wave -divider
|
||||
add wave -divider
|
||||
add wave /testbench_busybear/dut/uncore/HSELBootTim
|
||||
add wave /testbench_busybear/dut/uncore/HSELTim
|
||||
add wave /testbench_busybear/dut/uncore/HREADTim
|
||||
add wave /testbench_busybear/dut/uncore/dtim/HREADTim0
|
||||
add wave /testbench_busybear/dut/uncore/HREADYTim
|
||||
add wave -divider
|
||||
add wave -divider
|
||||
add wave /testbench_busybear/dut/uncore/HREADBootTim
|
||||
add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0
|
||||
add wave /testbench_busybear/dut/uncore/HREADYBootTim
|
||||
@ -89,8 +82,8 @@ add wave /testbench_busybear/dut/uncore/HRDATA
|
||||
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG
|
||||
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG
|
||||
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG
|
||||
add wave -divider
|
||||
# registers!
|
||||
add wave -divider
|
||||
# registers!
|
||||
add wave -hex /testbench_busybear/regExpected
|
||||
add wave -hex /testbench_busybear/regNumExpected
|
||||
add wave -hex /testbench_busybear/HWRITE
|
||||
@ -130,49 +123,49 @@ add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28]
|
||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29]
|
||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30]
|
||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31]
|
||||
add wave /testbench_busybear/InstrFName
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCD
|
||||
#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
|
||||
add wave /testbench_busybear/InstrDName
|
||||
#add wave -divider
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCE
|
||||
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE
|
||||
add wave /testbench_busybear/InstrEName
|
||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE
|
||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE
|
||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE
|
||||
#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE
|
||||
#add wave -divider
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCM
|
||||
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM
|
||||
add wave /testbench_busybear/InstrMName
|
||||
#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite
|
||||
#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
|
||||
#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
|
||||
#add wave -divider
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCW
|
||||
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
|
||||
add wave /testbench_busybear/InstrWName
|
||||
#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
|
||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW
|
||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
|
||||
#add wave -divider
|
||||
##add ww
|
||||
add wave -hex -r /testbench_busybear/*
|
||||
#
|
||||
#-- Set Wave Output Items
|
||||
#TreeUpdate [SetDefaultTree]
|
||||
#WaveRestoreZoom {0 ps} {100 ps}
|
||||
#configure wave -namecolwidth 250
|
||||
#configure wave -valuecolwidth 120
|
||||
#configure wave -justifyvalue left
|
||||
#configure wave -signalnamewidth 0
|
||||
#configure wave -snapdistance 10
|
||||
#configure wave -datasetprefix 0
|
||||
#configure wave -rowmargin 4
|
||||
#configure wave -childrowmargin 2
|
||||
#set DefaultRadix hexadecimal
|
||||
#
|
||||
#-- Run the Simulation
|
||||
run -all
|
||||
##quit
|
||||
add wave /testbench_busybear/InstrFName
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCD
|
||||
#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
|
||||
add wave /testbench_busybear/InstrDName
|
||||
#add wave -divider
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCE
|
||||
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE
|
||||
add wave /testbench_busybear/InstrEName
|
||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE
|
||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE
|
||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE
|
||||
#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE
|
||||
#add wave -divider
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCM
|
||||
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM
|
||||
add wave /testbench_busybear/InstrMName
|
||||
#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite
|
||||
#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
|
||||
#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
|
||||
#add wave -divider
|
||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCW
|
||||
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
|
||||
add wave /testbench_busybear/InstrWName
|
||||
#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
|
||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW
|
||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
|
||||
#add wave -divider
|
||||
##add ww
|
||||
add wave -hex -r /testbench_busybear/*
|
||||
#
|
||||
#-- Set Wave Output Items
|
||||
#TreeUpdate [SetDefaultTree]
|
||||
#WaveRestoreZoom {0 ps} {100 ps}
|
||||
#configure wave -namecolwidth 250
|
||||
#configure wave -valuecolwidth 120
|
||||
#configure wave -justifyvalue left
|
||||
#configure wave -signalnamewidth 0
|
||||
#configure wave -snapdistance 10
|
||||
#configure wave -datasetprefix 0
|
||||
#configure wave -rowmargin 4
|
||||
#configure wave -childrowmargin 2
|
||||
#set DefaultRadix hexadecimal
|
||||
#
|
||||
#-- Run the Simulation
|
||||
run -all
|
||||
##quit
|
||||
|
||||
@ -113,6 +113,6 @@ configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
|
||||
-- Run the Simulation
|
||||
#run 2000
|
||||
#run 4100
|
||||
run -all
|
||||
#quit
|
||||
|
||||
@ -100,7 +100,7 @@ module dmem (
|
||||
|
||||
assign lrM = MemReadM && AtomicM;
|
||||
assign scM = MemRWM[0] && AtomicM;
|
||||
assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM == ReservationPAdrW) && ReservationValidW;
|
||||
assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`XLEN-1:2] == ReservationPAdrW) && ReservationValidW;
|
||||
assign SquashSCM = scM && ~WriteAdrMatchM;
|
||||
always_comb begin // ReservationValidM (next valiue of valid reservation)
|
||||
if (lrM) ReservationValidM = 1; // set valid on load reserve
|
||||
|
||||
@ -84,9 +84,7 @@ module ahblite (
|
||||
typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype;
|
||||
statetype BusState, NextBusState;
|
||||
|
||||
always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) BusState <= #1 IDLE;
|
||||
else BusState <= #1 NextBusState;
|
||||
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
|
||||
|
||||
always_comb
|
||||
case (BusState)
|
||||
@ -102,7 +100,7 @@ module ahblite (
|
||||
else NextBusState = IDLE;
|
||||
INSTRREAD: //if (~HREADY & (MemReadM | MemWriteM)) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete
|
||||
if (~HREADY) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE;
|
||||
else NextBusState = IDLE; // if (InstrReadF still high)
|
||||
INSTRREADMEMPENDING: if (~HREADY) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete
|
||||
else if (MemReadM) NextBusState = MEMREAD;
|
||||
else NextBusState = MEMWRITE; // must be write if not a read. Don't return to idle.
|
||||
|
||||
@ -82,11 +82,11 @@ module flopenr #(parameter WIDTH = 8) (
|
||||
endmodule
|
||||
|
||||
// flop with enable, asynchronous load
|
||||
module flopenl #(parameter WIDTH = 8) (
|
||||
input logic clk, load, en,
|
||||
input logic [WIDTH-1:0] d,
|
||||
input logic [WIDTH-1:0] val,
|
||||
output logic [WIDTH-1:0] q);
|
||||
module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
|
||||
input logic clk, load, en,
|
||||
input TYPE d,
|
||||
input TYPE val,
|
||||
output TYPE q);
|
||||
|
||||
always_ff @(posedge clk, posedge load)
|
||||
if (load) q <= #1 val;
|
||||
|
||||
@ -116,7 +116,7 @@ module controller(
|
||||
if (InstrD[31:27] == 5'b00010)
|
||||
ControlsD = 22'b1_000_00_10_001_0_00_0_0_0_0_0_0_1_0; // lr
|
||||
else if (InstrD[31:27] == 5'b00011)
|
||||
ControlsD = 22'b1_101_01_01_110_0_00_0_0_0_0_0_0_1_0; // sc
|
||||
ControlsD = 22'b1_101_01_01_101_0_00_0_0_0_0_0_0_1_0; // sc
|
||||
else
|
||||
ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_1_0; // other atomic; decode later
|
||||
end else
|
||||
|
||||
@ -95,6 +95,14 @@ module testbench_busybear();
|
||||
end
|
||||
end
|
||||
|
||||
// initial loading of memories
|
||||
initial begin
|
||||
$readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3);
|
||||
$readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.uncore.dtim.RAM);
|
||||
$readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.imem.bootram, 'h1000 >> 3);
|
||||
$readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.imem.RAM);
|
||||
end
|
||||
|
||||
integer warningCount = 0;
|
||||
|
||||
//logic[63:0] adrTranslation[4:0];
|
||||
@ -154,10 +162,10 @@ module testbench_busybear();
|
||||
$display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
|
||||
`ERROR
|
||||
end
|
||||
if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
|
||||
force dut.hart.ieu.dp.regf.rf[i] = regExpected;
|
||||
release dut.hart.ieu.dp.regf.rf[i];
|
||||
end
|
||||
//if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
|
||||
// force dut.hart.ieu.dp.regf.rf[i] = regExpected;
|
||||
// release dut.hart.ieu.dp.regf.rf[i];
|
||||
//end
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -179,8 +187,8 @@ module testbench_busybear();
|
||||
|
||||
logic [`XLEN-1:0] readAdrExpected;
|
||||
|
||||
always @(dut.hart.MemRWM[1] or HADDR) begin
|
||||
if (dut.hart.MemRWM[1] && HADDR != dut.PCF) begin
|
||||
always @(dut.hart.MemRWM[1] or HADDR or dut.HRDATA) begin
|
||||
if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA != {64{1'bx}}) begin
|
||||
if($feof(data_file_memR)) begin
|
||||
$display("no more memR data to read");
|
||||
`ERROR
|
||||
@ -194,7 +202,7 @@ module testbench_busybear();
|
||||
end
|
||||
|
||||
if (((readMask & HRDATA) !== (readMask & dut.HRDATA)) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
|
||||
$display("warning %0t ps, instr %0d: HRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE);
|
||||
$display("warning %0t ps, instr %0d: ExpectedHRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE);
|
||||
warningCount += 1;
|
||||
`ERROR
|
||||
end
|
||||
@ -340,13 +348,40 @@ module testbench_busybear();
|
||||
always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin
|
||||
if(~HWRITE) begin
|
||||
#3;
|
||||
if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin
|
||||
if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin
|
||||
if (dut.PCF !== lastPCF) begin
|
||||
lastCheckInstrF = CheckInstrF;
|
||||
lastPC <= dut.PCF;
|
||||
lastPC2 <= lastPC;
|
||||
if (speculative && (lastPC != pcExpected)) begin
|
||||
speculative = ~equal(dut.PCF,pcExpected,3);
|
||||
if(dut.PCF===pcExpected) begin
|
||||
if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
|
||||
force CheckInstrF = 32'b0010011;
|
||||
release CheckInstrF;
|
||||
force dut.hart.ifu.InstrF = 32'b0010011;
|
||||
#7;
|
||||
release dut.hart.ifu.InstrF;
|
||||
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
|
||||
warningCount += 1;
|
||||
forcedInstr = 1;
|
||||
end
|
||||
else begin
|
||||
if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
|
||||
force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
|
||||
release CheckInstrF;
|
||||
force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
|
||||
#7;
|
||||
release dut.hart.ifu.InstrF;
|
||||
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
|
||||
warningCount += 1;
|
||||
forcedInstr = 1;
|
||||
end
|
||||
else begin
|
||||
forcedInstr = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if($feof(data_file_PC)) begin
|
||||
@ -359,21 +394,31 @@ module testbench_busybear();
|
||||
PCtext = {PCtext, " ", PCtext2};
|
||||
end
|
||||
scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF);
|
||||
if(CheckInstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
|
||||
CheckInstrF = 32'b0010011;
|
||||
$display("warning: NOPing out %s at PC=%0x", PCtext, dut.PCF);
|
||||
warningCount += 1;
|
||||
forcedInstr = 1;
|
||||
end
|
||||
else begin
|
||||
if(CheckInstrF[28:27] != 2'b11 && CheckInstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
|
||||
CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
|
||||
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
|
||||
if(dut.PCF === pcExpected) begin
|
||||
if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
|
||||
force CheckInstrF = 32'b0010011;
|
||||
release CheckInstrF;
|
||||
force dut.hart.ifu.InstrF = 32'b0010011;
|
||||
#7;
|
||||
release dut.hart.ifu.InstrF;
|
||||
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
|
||||
warningCount += 1;
|
||||
forcedInstr = 1;
|
||||
end
|
||||
else begin
|
||||
forcedInstr = 0;
|
||||
if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
|
||||
force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
|
||||
release CheckInstrF;
|
||||
force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
|
||||
#7;
|
||||
release dut.hart.ifu.InstrF;
|
||||
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
|
||||
warningCount += 1;
|
||||
forcedInstr = 1;
|
||||
end
|
||||
else begin
|
||||
forcedInstr = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
// then expected PC value
|
||||
|
||||
@ -42,6 +42,9 @@ module testbench();
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
//logic [31:0] InstrW;
|
||||
logic [`XLEN-1:0] meminit;
|
||||
string tests64a[] = '{
|
||||
"rv64a/WALLY-LRSC", "2110"
|
||||
};
|
||||
string tests64m[] = '{
|
||||
"rv64m/I-MUL-01", "3000",
|
||||
"rv64m/I-MULH-01", "3000",
|
||||
@ -328,9 +331,11 @@ string tests32i[] = {
|
||||
initial
|
||||
if (`XLEN == 64) begin // RV64
|
||||
tests = {tests64i};
|
||||
if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic};
|
||||
else tests = {tests, tests64iNOc};
|
||||
if (`M_SUPPORTED % 2 == 1) tests = {tests, tests64m};
|
||||
if (`C_SUPPORTED) tests = {tests, tests64ic};
|
||||
else tests = {tests, tests64iNOc};
|
||||
if (`M_SUPPORTED) tests = {tests, tests64m};
|
||||
if (`A_SUPPORTED) tests = {tests64a, tests};
|
||||
// tests = {tests64a, tests};
|
||||
end else begin // RV32
|
||||
tests = {tests32i};
|
||||
if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
|
||||
@ -375,6 +380,7 @@ string tests32i[] = {
|
||||
$readmemh(memfilename, dut.imem.RAM);
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
testName = tests[test];
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset = 1; # 42; reset = 0;
|
||||
end
|
||||
|
||||
@ -602,6 +608,30 @@ module instrNameDecTB(
|
||||
10'b1110011_101: name = "CSRRWI";
|
||||
10'b1110011_110: name = "CSRRSI";
|
||||
10'b1110011_111: name = "CSRRCI";
|
||||
10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W";
|
||||
else if (funct7[6:2] == 5'b00011) name = "SC.W";
|
||||
else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
|
||||
else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
|
||||
else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
|
||||
else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
|
||||
else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
|
||||
else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
|
||||
else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
|
||||
else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
|
||||
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
|
||||
else name = "ILLEGAL";
|
||||
10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D";
|
||||
else if (funct7[6:2] == 5'b00011) name = "SC.D";
|
||||
else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
|
||||
else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
|
||||
else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
|
||||
else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
|
||||
else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
|
||||
else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
|
||||
else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
|
||||
else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
|
||||
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
|
||||
else name = "ILLEGAL";
|
||||
10'b0001111_???: name = "FENCE";
|
||||
default: name = "ILLEGAL";
|
||||
endcase
|
||||
|
||||
Loading…
Reference in New Issue
Block a user