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149 Commits

Author SHA1 Message Date
Kevin Kim
354e1ca5c6 lints 2024-02-19 09:06:35 -08:00
Kevin Kim
ccf8d125b7 added updated dervlist 2024-02-19 09:01:44 -08:00
David Harris
ea14162c40
Merge pull request #625 from kevindkim723/shiftcorrectionfix 
added fd_rv32gc config
 2024-02-08 10:38:46 -08:00
Kevin Kim
c921a3b55c added fd_rv32gc config 2024-02-08 10:10:51 -08:00
Rose Thompson
662e848ad8 Updated deriv list to correct TWOBIT predictor configs. 2024-02-06 22:15:41 -06:00
David Harris
0bc01fffbb fixed two-bit bpred configurations in derivlist.txt 2024-02-06 16:33:38 -08:00
David Harris
d71efedab5
Merge pull request #619 from ross144/main 
Merged all regression tests except imperas linux boot into testbench.sv.
 2024-02-06 16:19:42 -08:00
Rose Thompson
da65928f04 Fixed issue with branch deriv configs. 2024-02-06 16:07:41 -06:00
David Harris
dfee790ad7 Fixed derivative generation when derivs don't already exist. Fixed lint to print success when no failures. Added Zfh fma tests. Some fp tests not running yet. 2024-02-06 12:35:56 -08:00
David Harris
b70eb80f8e simplified derivative generation 2024-02-04 19:29:53 -08:00
Rose Thompson
a2f8d70342 Updated branch predictor derivative configs. 2024-02-04 16:53:47 -06:00
David Harris
49714cb282 Fixed assertions to throw fatal error, improved nightly regression to have passing cases 2024-01-31 21:39:18 -08:00
David Harris
a4ca024025 Lint progress 2024-01-31 20:03:14 -08:00
David Harris
111f592613 factor divsqrt out of floating-point test cases to run on more derived configs 2024-01-31 14:52:15 -08:00
David Harris
2af9282bbc Starting to add nightly regression capability using derived configs 2024-01-31 13:18:00 -08:00
David Harris
0abfe5cb55 Fixed some lint errors in derived configs 2024-01-31 11:39:59 -08:00
David Harris
0828250596 Removed unused rv64fpquad config 2024-01-30 09:52:23 -08:00
David Harris
bf7e20e846 IEEE754 derivatives for testfloat 2024-01-30 09:49:27 -08:00
David Harris
f37c7bb1f6 Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this 2024-01-30 06:27:18 -08:00
David Harris
32c102d89a All deriv tests generated, use sim/make deriv 2024-01-29 14:34:42 -08:00
David Harris
d52d2d7983 Initial derivgen working 2024-01-29 11:22:34 -08:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
David Harris
7215f48dda coverage improvements: fixing problems running ImperasDV on coverage tests 2024-01-23 22:21:01 -08:00
David Harris
d801bf5d6c
Revert "more shiftcorrection bug fixes" 2024-01-21 10:41:14 -08:00
Kevin Kim
1459943a75 more shiftcorrection bug fixes 2024-01-21 10:08:48 -08:00
Kevin Kim
991f1494d3
Merge branch 'openhwgroup:main' into shiftcorrectiondebug 2024-01-21 08:27:33 -08:00
Kevin Kim
3241802441 fixed bug in CORRSHIFTSZ param 2024-01-21 08:25:17 -08:00
David Harris
9260d3c424 Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test 2024-01-18 22:46:07 -08:00
David Harris
17c9be7695 Cleanup typos, remove Zicond from riscof until it is working 2024-01-18 21:36:52 -08:00
David Harris
60e09965d5 Enabled Zfh support in rv64gc 2024-01-16 11:14:43 -08:00
David Harris
bb3a7850c4 Simplified floating-point parameters in config-shared 2024-01-15 17:48:41 -08:00
David Harris
da4eca4854 Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int. 2024-01-15 13:24:57 -08:00
Rose Thompson
ba95e5fafd Reduced the rv64gc config to 128MiB memory. 2024-01-12 20:01:05 -06:00
David Harris
9eb6d9c8b8 Added Zicond support 2024-01-11 07:37:15 -08:00
David Harris
dc3284049c Rolled back B extension in rv32/64gc MISA because imperasDV isn't matching 2023-12-21 11:03:50 -08:00
David Harris
09ea6e6485 Set B in MISA for rv32gc and rv64gc 2023-12-20 16:29:31 -08:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
Rose Thompson
b02bd6c835 Finally we got the wally tracer working with linux. 2023-11-21 13:45:55 -06:00
Rose Thompson
b137759b45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
3594c08d4b Modified linux imperas tests to 
1. enable zicclsm
2. enable logging at 7000 ms
 2023-11-20 10:30:35 -06:00
David Harris
b692c913c4 Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile 2023-11-18 20:56:50 -08:00
David Harris
acc2db256f turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep 2023-11-17 20:25:24 -08:00
David Harris
96556064a4 Restored RV64GC BPRED_SIZE=10 for consistent synthesis results 2023-11-17 18:31:44 -08:00
David Harris
fb135c957c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-14 15:19:22 -08:00
David Harris
5e9157244b Restored Zfh to 0 for rv64gc because it breaks floating-point tests 2023-11-14 15:18:16 -08:00
Rose Thompson
bf51948616 Merge pull request #474 from davidharrishmc/dev 
FP and synthesis cleanup
 2023-11-14 12:03:01 -08:00
David Harris
8ba0336c6f Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e 2023-11-14 11:01:58 -08:00
David Harris
5211b3aa85 Merge pull request #473 from ross144/main 
Missed a few files in the last pull request.  Removes the fpga config from the linter.
 2023-11-14 10:15:31 -08:00
Rose Thompson
fdb75203cb Added cbop to to rv32gc. 2023-11-14 10:55:22 -06:00
David Harris
a77bea9954 Merge pull request #472 from ross144/main 
Merge Zicclsm into main branch and removes the FPGA config.  FPGA makefile now automatically creates the config when building
 2023-11-14 08:34:06 -08:00