Marcus Mellor
eeedc26908
soc: Add shallow=true to basejump_stl submodule
2024-03-27 10:16:31 -05:00
Marcus Mellor
1677dcc7d5
soc: Fix basejump_stl submodule path
2024-03-27 10:16:31 -05:00
Marcus Mellor
60108a3462
soc/src/fifo/fifo.sv: Fix missing parameter
2024-03-27 10:16:31 -05:00
Marcus Mellor
74a4d895e8
soc/src/bsg_dmc_ahb.sv: Fix incorrect parameters
2024-03-27 10:16:31 -05:00
Marcus Mellor
e33683c72f
soc/src/bsg_dmc_ahb.sv: Fix syntax errors
2024-03-27 10:16:31 -05:00
Marcus Mellor
62804195f8
soc: organize SoC sources
2024-03-27 10:16:31 -05:00
Marcus Mellor
f492a9a6c8
soc/fifo: Add copyright headers
2024-03-27 10:16:31 -05:00
Marcus Mellor
1799823cf8
uncore: Revert changes to uncore.sv
...
Previously I made changes to uncore.sv to enable external RAM with
the bsg_dmc memory controller. As it turns out, these changes were
unnecessary as I should have implemented the bsg_dmc interface at
the toplevel external AHB bus.
2024-03-27 10:16:31 -05:00
Marcus Mellor
efc3bc9615
soc: Move SoC sv to a new folder
2024-03-27 10:16:31 -05:00
Marcus Mellor
dec30b4d99
uncore: Add fifo
2024-03-27 10:16:31 -05:00
Marcus Mellor
b05893647f
uncore: Add bsg_dmc and expose DDR PHY interface
2024-03-27 10:16:31 -05:00
Marcus Mellor
7aef43372d
uncore: Add bsg_dmc memory controller to AHB bus
2024-03-27 10:16:31 -05:00
David Harris
68fe8270f3
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-03-26 18:36:47 -07:00
Rose Thompson
7c3e93bb2c
added lpddrtest.
2024-03-26 18:42:48 -05:00
David Harris
ce290e5c29
Merge pull request #694 from quswarabid/bringup_ISACOV
...
ISACOV is functioning - March 27, 2024
2024-03-26 16:31:05 -07:00
Quswar Abid
21dd4649de
ISACOV is functioning - March 27, 2024
2024-03-26 14:17:41 -07:00
David Harris
4eb7de7381
Removed Zfh tests from wally-riscv-arch-test now that they are available in riscv-arch-test
2024-03-26 13:58:59 -07:00
David Harris
34219756f4
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-03-26 13:57:10 -07:00
David Harris
a3329d9c49
Merge pull request #692 from ross144/main
...
Fixed #689 caused by removal of #1 delays. For some reason the #1 were not removed from cacheLRU.sv.
2024-03-26 13:56:55 -07:00
slmnemo
282f545d67
Added generated directory linux-testvectors to gitignore
2024-03-26 10:32:28 -07:00
slmnemo
fcd98232d3
Merge branch 'nightly-regression' of github.com:slmnemo/cvw into linux_local
2024-03-26 10:30:33 -07:00
slmnemo
6fbac9ec97
Merge branch 'main' of https://github.com/openhwgroup/cvw into nightly-regression
2024-03-26 10:29:00 -07:00
slmnemo
efb68e7eeb
Added dumptvs function to Linux makefile to create linux-testvectors in /opt/riscv directory
2024-03-26 10:28:50 -07:00
Rose Thompson
5b4d3f49b0
Fixed #689 caused by removal of #1 delays. For some reason the #1 were not removed from cacheLRU.sv.
2024-03-26 12:26:03 -05:00
David Harris
6688577bc4
Fixed fcvt test macro
2024-03-25 12:21:15 -07:00
David Harris
0caab3c0c9
Removed delays from cacheLRU and testbench
2024-03-25 12:20:25 -07:00
David Harris
690338b758
Incorporated fixed fcvt.h.l* instructions; they now run in the testbench
2024-03-25 06:08:27 -07:00
Rose Thompson
947e4bb027
Merge pull request #688 from davidharrishmc/dev
...
Cleanup
2024-03-24 21:03:21 -05:00
David Harris
fc158689ad
Shared amoalu max/min comparator hardware and removed input sign extend muxes
2024-03-24 17:15:46 -07:00
David Harris
f0b29d3083
AMO max/min comparator optimization
2024-03-24 17:05:32 -07:00
David Harris
5e53aa4de7
Updated tool chain installation instructions and added a script for docker installation
2024-03-24 15:19:36 -07:00
David Harris
2d60b48db4
Added #! so coremark_sweep.py is executable
2024-03-24 14:42:09 -07:00
David Harris
b3661a0af4
Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead
2024-03-24 12:31:49 -07:00
David Harris
54b54c900c
Merge pull request #686 from jordancarlin/main
...
Update testbench-fp to support Zfa in FPU modules
2024-03-23 20:13:04 -07:00
Jordan Carlin
d580d7af5d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-03-23 17:56:23 -07:00
Jordan Carlin
fd97108dc3
Update testbench-fp to support Zfa in FPU modules
2024-03-23 17:55:59 -07:00
David Harris
bae52cf13d
Merge pull request #678 from Karl-Han/latest
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[Resolved Conflict] Remove all #delay from non-testbench
2024-03-23 15:18:04 -07:00
Rose Thompson
91919150a9
Merge pull request #683 from kevindkim723/update_derived_configs
...
Update derived configs
2024-03-22 13:12:00 -05:00
Rose Thompson
b1a933f4f2
Merge pull request #685 from Shreesh-Kulkarni/patch-2
...
Patched coremark_sweep.py. The script now runs for both 32 and 64bit.
2024-03-22 13:11:41 -05:00
Shreesh Kulkarni
9976f7e617
Update coremark_sweep.py
2024-03-22 23:09:14 +05:30
Shreesh Kulkarni
984ed42f6a
Patched coremark_sweep.py. The script now runs for both 32 and 64bit.
2024-03-22 23:05:24 +05:30
slmnemo
8592883100
Merge branch 'main' of github.com:slmnemo/cvw into linux_local
2024-03-21 15:55:58 -07:00
Kevin Kim
c8b84ebbc5
regression-wally -softfloat with updated derived configs
2024-03-20 09:58:14 -07:00
Kevin Kim
ccf2c270a1
Merge branch 'update_derived_configs' of https://github.com/kevindkim723/cvw into update_derived_configs
2024-03-20 09:54:08 -07:00
Kevin Kim
ac00eaf322
added some missing derived configs
2024-03-20 09:50:52 -07:00
Rose Thompson
d6b3fc0320
Merge pull request #682 from Shreesh-Kulkarni/patch-1
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Python Script for Coremark-sweep of 32-bit configurations of Wally.
2024-03-20 09:50:25 -05:00
Rose Thompson
e97c2cbd83
Merge pull request #676 from davidharrishmc/dev
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Incorporated Zfa and Zfh tests into wally-riscv-arch-test, mcmodel example code, minor cleanup
2024-03-20 09:45:39 -05:00
Shreesh Kulkarni
d54ebc2785
added authorship and copyright comments
2024-03-20 20:06:45 +05:30
Rose Thompson
a884c04b62
Merge pull request #679 from kevindkim723/extract_arch_test_fix
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fixed bug in intdivrem test vector extraction
2024-03-20 09:27:45 -05:00
Rose Thompson
8f9a79d792
Merge pull request #680 from Thomas-J-Kidd/updating-ease-of-usage
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Updating ease of usage of nightly_build.py
2024-03-20 09:27:02 -05:00
