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Merge pull request #692 from ross144/main

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Fixed #689 caused by removal of #1 delays.  For some reason the #1 were not removed from cacheLRU.sv.
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David Harris 2024-03-26 13:56:55 -07:00 committed by GitHub
commit a3329d9c49
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1 changed files with 2 additions and 2 deletions
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4
src/cache/cacheLRU.sv vendored
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@ -149,8 +149,8 @@ module cacheLRU
for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize
else if(CacheEn) begin
// Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value
if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = #1 NextLRU;
else CurrLRU = #1 LRUMemory[CacheSetTag];
if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU;
else CurrLRU = LRUMemory[CacheSetTag];
if(LRUWriteEn) LRUMemory[PAdr] = NextLRU;
end
end