Ross Thompson
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3b612d6201
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Possible fixes for earily messup of rv32ic and rv64ic configs.
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2022-08-25 14:42:08 -05:00 |
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Ross Thompson
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f67010c688
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 14:40:52 -05:00 |
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David Harris
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bc0c7d0cd8
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Cleaned up SelBusWord
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2022-08-25 11:18:13 -07:00 |
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David Harris
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c442dea173
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Removed M sufix from busdp signals
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2022-08-25 11:13:01 -07:00 |
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David Harris
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48f346baf8
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Renamed LSUFunct3M to Funct3 in busdp
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2022-08-25 11:08:12 -07:00 |
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David Harris
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9bada9c14a
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Renaming LSU signals from busdp
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2022-08-25 11:05:10 -07:00 |
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David Harris
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3ba961d1a8
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renamed BusBuffer to FetchBuffer
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2022-08-25 10:44:39 -07:00 |
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David Harris
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dda3b441d7
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Continued busdp/ebu simplification
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2022-08-25 10:20:02 -07:00 |
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David Harris
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19fe6d106c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 09:52:49 -07:00 |
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David Harris
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aba914ea5e
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Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
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2022-08-25 09:52:08 -07:00 |
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Ross Thompson
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e605ef57dc
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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b0aea77b20
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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Ross Thompson
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01a7718471
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Added generate around ebu.
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2022-08-25 09:24:13 -05:00 |
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Ross Thompson
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ad485fe591
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 09:03:34 -05:00 |
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Ross Thompson
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701324eeb8
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Updated ila signals.
Improve fpga wave config.
added back in the fpga preload.
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2022-08-25 09:03:29 -05:00 |
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David Harris
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ae0702d129
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Renamed DCache to Cache in busdp/busfsm signal interface
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2022-08-25 06:21:22 -07:00 |
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David Harris
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3500286803
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Cleanup typos
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2022-08-25 04:32:19 -07:00 |
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David Harris
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db5c941d6f
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Minor name cleanups
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2022-08-25 04:28:25 -07:00 |
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David Harris
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1206b388c7
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Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
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2022-08-25 04:06:27 -07:00 |
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David Harris
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f7209627c2
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removed simpleram and modified dtim to use bram1p1rw
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2022-08-25 03:39:57 -07:00 |
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David Harris
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562be633ab
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Stripped write capaibilty out of rom_ahb
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2022-08-24 17:23:08 -07:00 |
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David Harris
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a131e1f17a
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Added ROM module and moved memories into generic/mem
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2022-08-24 17:03:22 -07:00 |
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David Harris
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6785644fb8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-24 16:30:28 -07:00 |
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David Harris
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b21b91234b
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Ram cleanup
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2022-08-24 16:30:25 -07:00 |
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Ross Thompson
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d10edfa5e0
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No longer need wally-pipelined-fpga.do.
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2022-08-24 18:10:45 -05:00 |
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Ross Thompson
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769af32f2a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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fc22e807e2
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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4a371b6829
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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d23b309e0d
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Fixed lint errors with bram wrapper.
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2022-08-24 13:19:23 -05:00 |
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Ross Thompson
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51adf6cba9
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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bcb52acfba
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bram synthesis test
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2022-08-23 19:34:45 -07:00 |
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David Harris
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3fdcc363d5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-24 00:09:20 +00:00 |
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David Harris
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1acbbbbad9
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Rolled back synth scripts to fff91ae commit before Madeleine's modifications to write config files; the modified version is failing right away with trouble copying configs
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2022-08-24 00:09:16 +00:00 |
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Ross Thompson
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e671291c72
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 18:57:43 -05:00 |
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Ross Thompson
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e4cbb43c67
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 18:52:15 -05:00 |
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Ross Thompson
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642dc170d7
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Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.
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2022-08-23 18:51:11 -05:00 |
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David Harris
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5eebd521c5
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Fixed FPU-IEU forwarding stall
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2022-08-23 14:14:41 -07:00 |
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David Harris
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d72068d582
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Only stall FPU to IEU on convert instructions with dependencies
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2022-08-23 12:57:18 -07:00 |
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David Harris
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05aa18fe14
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Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
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2022-08-23 12:17:19 -07:00 |
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David Harris
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d19fc99bf0
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Simplify IEU-FP datapath
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2022-08-23 11:16:36 -07:00 |
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David Harris
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f72d07adce
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Improved illegal instruction checking in FPU
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2022-08-23 11:08:02 -07:00 |
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David Harris
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c61dba6192
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Fixed LSU typos
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2022-08-23 10:23:08 -07:00 |
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David Harris
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2a1bd53663
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 10:14:59 -07:00 |
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David Harris
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029aecabf7
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typo in srtfsm
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2022-08-23 10:14:54 -07:00 |
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Katherine Parry
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fe0c6afe58
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-23 16:36:32 +00:00 |
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Katherine Parry
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4e33ead413
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renamed rounding bits to L,G,R,S and fixed lint warning
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2022-08-23 16:36:20 +00:00 |
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Ross Thompson
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8d4301e2f6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 11:15:04 -05:00 |
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Ross Thompson
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20ba6fd19c
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Reversed order of supported sized in adrdecs.
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2022-08-23 11:14:53 -05:00 |
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Ross Thompson
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5efec3b1f3
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Replaced FPU data replicaiton on WriteData bus with 0 extention.
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2022-08-23 10:46:03 -05:00 |
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Ross Thompson
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aa5cbab0d8
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Replaced LSU data replication with 0 extention.
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2022-08-23 10:43:47 -05:00 |
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