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4,212 Commits 4 Branches 2 Tags 53 MiB
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1335 Commits

Author SHA1 Message Date
Ross Thompson
3361a06c62 Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 16:31:07 -05:00
Ross Thompson
5d2b299182 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
c1de88d929 Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 13:54:48 -05:00
Ross Thompson
4d60d9a840 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
David Harris
41448663b9 Initial radix 4 square root debuggin 2022-09-01 16:57:57 -07:00
Ross Thompson
055b55402f clean up subword write. 2022-09-01 17:55:19 -05:00
David Harris
5e26bcced1 Fixed lint errors in square root and improved waveforms in testfloat 2022-09-01 15:49:13 -07:00
Ross Thompson
eae56a890c marked possible improvement to ahb bus fsms. 2022-08-31 23:57:08 -05:00
David Harris
199296dd03 fdiv debug 2022-08-31 14:26:31 -07:00
Ross Thompson
7598fbcb3b Reduced busfsm to 3 states! 2022-08-31 16:11:59 -05:00
Ross Thompson
6f3dad8207 Simplified. 2022-08-31 15:40:56 -05:00
Ross Thompson
0f2315e8a1 more renaming. 2022-08-31 14:52:06 -05:00
Ross Thompson
12d1ef2144 More renaming. 2022-08-31 14:49:08 -05:00
Ross Thompson
c03b202ab0 Moved files. 
Encapsulated ahbinterface.
 2022-08-31 14:45:01 -05:00
Ross Thompson
f2f1169a04 Renamed AHBCachebusdp to abhcacheinterface. 2022-08-31 14:12:19 -05:00
Ross Thompson
1b339f0547 Moved files around. 2022-08-31 14:08:06 -05:00
Ross Thompson
cc7b35b831 Merge branch 'multimanager' into main 2022-08-31 13:10:22 -05:00
Ross Thompson
10817f7885 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 13:10:04 -05:00
David Harris
09456db445 Checking in radix 4 square root with qsel, fgen, softc, but not working 2022-08-31 10:54:50 -07:00
Ross Thompson
0d3f03ac06 Major cleanup of multimanager. 2022-08-31 12:40:25 -05:00
Ross Thompson
77cc549cfa Cleanup multimanager. 2022-08-31 12:04:44 -05:00
Ross Thompson
f3d611c686 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 11:38:29 -05:00
Ross Thompson
eaa9cbda46 cleanup of multimanager. 2022-08-31 11:38:06 -05:00
Ross Thompson
a0f681944c More Cleanup. 2022-08-31 11:21:02 -05:00
Ross Thompson
8156109add More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
4b167ad21e More simplifications. 2022-08-31 10:45:16 -05:00
Ross Thompson
a93c5b0f0a Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier. 2022-08-31 10:36:30 -05:00
Ross Thompson
ed2a9225ea Removed unused old versions of the bus controllers. 2022-08-31 09:51:54 -05:00
Ross Thompson
89f13370e2 Removed old signals. 2022-08-31 09:50:39 -05:00
DTowersM
48a1abf06f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-31 00:18:04 +00:00
DTowersM
bdeb5c6509 fixed qrduino keyerror in embench test 2022-08-31 00:17:58 +00:00
Ross Thompson
5409501ca6 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
cce3fdd0e3 Updates to wave file. 2022-08-30 17:34:36 -05:00
Ross Thompson
8b9f30c91a more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
fab3a2b791 Temporary commit. 2022-08-30 15:40:42 -05:00
Ross Thompson
315f662eb9 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c Progress. 2022-08-30 14:17:00 -05:00
David Harris
e1760dde55 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
Ross Thompson
8cf3c7b352 new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
Ross Thompson
a2220fc142 Have a rough working multi manager! 2022-08-29 17:11:27 -05:00
Ross Thompson
f5584bb41c Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. 2022-08-29 17:04:53 -05:00
David Harris
28db4fdc70 commented out lines to have divider work again 2022-08-29 13:01:32 -07:00
David Harris
87b77658f2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 12:01:13 -07:00
David Harris
a6efbb3fda Initial FDIVSQRT simplification working 2022-08-29 12:01:09 -07:00
Ross Thompson
233777f744 Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. 2022-08-29 13:01:24 -05:00
Ross Thompson
e805f33f4e Typo. 2022-08-29 11:40:35 -05:00
Ross Thompson
dceaf6e4e3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 11:38:37 -05:00
Ross Thompson
e7de0e033e Added comments about planned changes. 2022-08-29 09:48:00 -05:00
David Harris
a82cf3d0ba Simplify FSM 2022-08-29 04:32:27 -07:00
David Harris
7856f08e1d Renamed special case 2022-08-29 04:29:58 -07:00
David Harris
7d4e85bf21 Separated out radix 2 and radix 4 stages into different modules 2022-08-29 04:26:14 -07:00
David Harris
2788022c22 renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
Ross Thompson
7b76fbaa9a Removed ignore request from busfsm. 2022-08-28 21:12:27 -05:00
Ross Thompson
122c88ee46 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
5e63af5887 Reordered the adrdecs. 2022-08-28 13:38:57 -05:00
Ross Thompson
dd7736cb93 Possible fix. 2022-08-28 13:10:47 -05:00
Ross Thompson
a81fcc6b4b Partial fix to bus + dtim. 2022-08-27 23:44:17 -05:00
David Harris
f2517f8290 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
60b673cafd Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus 2022-08-27 05:31:56 -07:00
David Harris
4aa30c48aa fixed wally-config 2022-08-26 22:13:10 -07:00
David Harris
37f0b52520 Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
David Harris
d0dbc74492 Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs 2022-08-26 21:29:26 -07:00
David Harris
2b241f8bbd Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
David Harris
03e731b3ff Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
f0b4f69b65 Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
David Harris
812158aeee Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
95dd50a567 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
David Harris
ca6837f597 Fixed endian swapping on bus only 2022-08-26 19:58:04 -07:00
David Harris
5f37e16b62 Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
David Harris
671ea60f3e lsu simplification 2022-08-25 18:52:42 -07:00
David Harris
ec2c6d4fcb busfsm simplified 2022-08-25 18:36:53 -07:00
David Harris
f262abb5c3 Removed unused signals 2022-08-25 18:34:39 -07:00
David Harris
b73286ece6 Removed unused signals 2022-08-25 18:30:46 -07:00
David Harris
949e76bc83 Removed UncachedBusRead and UncachedBusWrite 2022-08-25 18:24:39 -07:00
David Harris
e39694694c Restored ahbtranstype 2022-08-25 18:22:26 -07:00
David Harris
83d3782f2c Removed ahbtranstype 2022-08-25 18:21:45 -07:00
David Harris
543fbd1fa9 Removed WordCountFlag 2022-08-25 18:21:18 -07:00
David Harris
d118fcbde8 Removed UncachedAccess 2022-08-25 18:20:52 -07:00
David Harris
bac95823b6 Removed UncachedRW 2022-08-25 18:19:41 -07:00
David Harris
cfcde754c3 Removed CacheBusAck 2022-08-25 18:17:34 -07:00
David Harris
9bc62ce124 Removed SelUncachedAdr 2022-08-25 18:15:59 -07:00
David Harris
f39e62eeea Removed Cache_Enabled 2022-08-25 18:13:34 -07:00
David Harris
5bfaf31df0 Removed STATE_BUS_FETCH and STATE_BUS_WRITE 2022-08-25 18:12:09 -07:00
David Harris
85e93e2bb7 Removed CacheFetchLine and CacheWriteLine 2022-08-25 18:10:15 -07:00
David Harris
23a102b1b9 Removed CountEn 2022-08-25 18:05:44 -07:00
David Harris
e485e986a5 Removed wordcount 2022-08-25 18:04:49 -07:00
David Harris
69dff87feb Added buscachefsm for system with bus and cache 2022-08-25 18:01:01 -07:00
David Harris
5340c45dfc Separated busdp for cache from simpler logic for no cache 2022-08-25 17:54:04 -07:00
David Harris
9a92bfe095 Simplified swbytemask 2022-08-25 17:32:16 -07:00
David Harris
eb753b3b3f FIxed wallypipelinedsoc merge conflict 2022-08-25 15:36:47 -07:00
David Harris
902d2067ba Removed delayed AHB signals from top level 2022-08-25 15:34:14 -07:00
Ross Thompson
db635e3ad2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
Ross Thompson
8c8b95ecf5 Finally resolved the issues with the rv32ic and rv64ic configurations. 2022-08-25 16:00:55 -05:00
Ross Thompson
5c2bc20dbd Almost fixed issues with irom and dtim address selection. 2022-08-25 15:52:25 -05:00
David Harris
302a7fa294 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
179aec3616 Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
David Harris
07225cabb7 Fixed brom name 2022-08-25 12:48:00 -07:00
Ross Thompson
d23888407b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:45:02 -05:00
David Harris
1226b2889e ahblite cleanup 2022-08-25 12:44:25 -07:00
Ross Thompson
3b612d6201 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00