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Author SHA1 Message Date
James Stine
345c8ce08d temporary assignment of JTAG ID 2024-06-04 11:23:14 -05:00
James Stine
ae4900698e fix operator for ir and rad 2024-06-04 10:59:04 -05:00
James Stine
bdbd310bb4 fix operator for dm.sv 2024-06-04 10:57:56 -05:00
James Stine
1deb44b0fc fix operator for tap.sv 2024-06-04 10:56:44 -05:00
James Stine
5b50fcd4f4 update two files tha thad repeated lines in them 2024-06-04 09:25:41 -05:00
Matthew
2e0c286017 cleanup, rename python scripts 2024-06-03 23:21:40 -05:00
Matthew
0a6e7080dc Merge branch 'main' of https://github.com/stineje/cvw 2024-06-03 22:25:58 -05:00
Matthew
bc36edece2 clean up repo 2024-06-03 22:21:02 -05:00
James Stine
e49ca99c9d fix controller typo 2024-06-03 17:39:11 -05:00
James Stine
45af9398cd update ieu 2024-06-03 17:37:30 -05:00
James Stine
fc45fb8669 fix csr.sv 2024-06-03 17:27:40 -05:00
James Stine
3864a7f798 missing privileged.sv 2024-06-03 17:25:32 -05:00
James Stine
5a03fbee97 add flopenrs back 2024-06-03 17:13:02 -05:00
James Stine
2c2d5d888c fix missing paramter-defs.vh 2024-06-03 17:11:00 -05:00
James Stine
36c77af995 fix missing config-shared.vh 2024-06-03 17:07:19 -05:00
James Stine
0bb6a8866a fix missing input/output on debug module for lsu 2024-06-03 17:04:31 -05:00
James Stine
f5e01bea20 delete duplicate 2024-06-03 17:00:49 -05:00
James Stine
6a7f145de2 fix name of DSCR that I mistakenly made 2024-06-03 16:42:05 -05:00
James Stine
77ec3d58c6 seed debug module for Wally 2024-06-03 16:37:13 -05:00
David Harris
f73ebc1b45
Merge pull request #820 from ross144/main 
Updated spill logic to match textbook.
 2024-06-02 23:58:41 +02:00
Rose Thompson
b45b7ff7d6 Signal name changes to match book. 2024-06-02 16:32:25 -05:00
Rose Thompson
731e1fe08f Updated spill logic to reflect changes in textbook. 2024-06-02 15:48:42 -05:00
David Harris
b9d177edc4
Merge pull request #819 from ross144/main 
wsim now supports directories
 2024-06-01 18:57:17 +02:00
Rose Thompson
3da62558ec Updated readme. 2024-06-01 11:12:30 -05:00
Rose Thompson
2382677f8f Got the directory mode wsim working! 2024-06-01 10:56:37 -05:00
Rose Thompson
224b8469ab Updated readme to reflect changes to wsim. 2024-06-01 09:58:10 -05:00
Rose Thompson
a78093274c Simplified wsim so it automatically figures out if the second parameter is a testsuite or an elf file. 2024-06-01 09:56:50 -05:00
Rose Thompson
2a6c5a158f Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-06-01 09:50:18 -05:00
Rose Thompson
9ed78b5f08
Merge pull request #818 from JacobPease/main 
Added true bootloader to fpga/zsbl directory.
 2024-05-31 15:34:08 -05:00
Jacob Pease
7a417d7a6c Added true bootloader to fpga/zsbl directory. 2024-05-31 15:28:25 -05:00
Rose Thompson
24ba51370a
Merge pull request #817 from JacobPease/main 
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
 2024-05-30 16:16:05 -05:00
Jacob Pease
3f7659c8ad Removed old fpgaTop.v file. 2024-05-30 16:15:19 -05:00
Jacob Pease
6bf43ebe61 Merge branch 'main' of github.com:openhwgroup/cvw 2024-05-30 15:48:31 -05:00
Jacob Pease
7ecd1c7d5f The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
Rose Thompson
f4626d5b06 Fixed bug so that wsim can start logging after a given number of instructions. 2024-05-29 14:50:09 -05:00
Rose Thompson
84946919a4 Changed name CacheWriteData to WriteData. 2024-05-28 18:00:39 -05:00
Rose Thompson
273b41df99 Changed name of cache parameter NUMLINES to NUMSETS to better match book. 2024-05-28 17:55:43 -05:00
David Harris
44f25186c6
Merge pull request #816 from ross144/main 
Merges support for functional coverage into wally.do and testbench.sv
 2024-05-28 21:54:37 +02:00
Rose Thompson
a88d5f403b Functional coverage works with wally.do 2024-05-28 14:02:54 -05:00
Rose Thompson
0c5b70c40a It's a bit hacky. But I've got functional coverage working with our wally.do script and testbench.sv. 2024-05-28 13:54:48 -05:00
Rose Thompson
48fd365b9d Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage. 2024-05-28 13:00:17 -05:00
Rose Thompson
4a1e856b18 Almost working functional coverage in wally.do 
riscvISACOV is now loading, but for some reason I still cannot get it to record anything.
Instead it is just logging the instructions.
 2024-05-27 18:15:12 -05:00
Rose Thompson
92ee56c1a1 Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV. 
testbench.sv was missing the trace2cov instance.
 2024-05-27 17:25:20 -05:00
Rose Thompson
4c0261fd2c Closer. Needed to reorder includes and defines. 2024-05-27 15:37:16 -05:00
Rose Thompson
ff611016c7 Closer? 2024-05-27 14:11:02 -05:00
Rose Thompson
26c6eec832 Getting closer to functional coverage integration. 2024-05-27 13:20:18 -05:00
Rose Thompson
2985cfb7eb Preliminary work to merge functional coverage into wally.do. 2024-05-27 11:59:13 -05:00
Rose Thompson
c9b59c8b99
Merge pull request #815 from quswarabid/covergen 
Covergen
 2024-05-27 10:42:29 -05:00
Quswar Abid
997b5901cc sb types are all passing, loaditypes are not! 2024-05-27 04:27:50 -07:00
Quswar Abid
1bf9b13953 added some sb types 2024-05-27 03:58:38 -07:00