David Harris
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3407b63c8a
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Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
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2021-10-23 06:15:26 -07:00 |
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James E. Stine
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129ef03b2d
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Fix fpdivsqrt lint error on CPA for convergence
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2021-10-20 17:46:13 -05:00 |
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David Harris
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687703f0d8
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removed .* from wallypipeliendsoc
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2021-10-20 13:49:18 -07:00 |
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James E. Stine
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7536e0a2ee
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Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
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2021-10-20 12:00:41 -05:00 |
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James E. Stine
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ed179b0bd9
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Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
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2021-10-19 12:09:43 -05:00 |
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James E. Stine
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b65a4bd040
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Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
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2021-10-19 11:58:06 -05:00 |
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David Harris
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8d08ca6a1e
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Changed some flops to settable
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2021-10-18 17:05:29 -07:00 |
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David Harris
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df0b65e483
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replaced flopenl with flopenr when clearing to 0
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2021-10-18 16:53:18 -07:00 |
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David Harris
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d0b9ebd2ef
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-18 15:44:31 -07:00 |
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David Harris
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47f7a5db9c
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Fixed multiplier and pointed arch tests to new path in addins
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2021-10-18 15:43:59 -07:00 |
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Ross Thompson
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d8d414665c
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fixed issues with dc shell not liking modules with parameters without default values.
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2021-10-18 17:24:15 -05:00 |
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James E. Stine
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d895fd7ee5
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Sanitization some more on mult_cs.sv
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2021-10-18 05:24:16 -05:00 |
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James E. Stine
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aafa988ca2
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Update some on mult_cs and delete DW02_mult.v
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2021-10-18 05:06:49 -05:00 |
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James E. Stine
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5a1835622c
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Add hacky hand-made carry/save multiplier - will improve
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2021-10-16 10:37:29 -05:00 |
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Katherine Parry
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33e5a078bf
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cvtfp module documented
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2021-10-14 15:25:31 -07:00 |
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James E. Stine
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6b30adb309
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Clean up some signals - beautification onging
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2021-10-14 17:12:00 -05:00 |
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Skylar Litz
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395e070917
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-13 15:38:32 -07:00 |
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Skylar Litz
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d639222519
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add StallM signal back to DivStartE control
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2021-10-13 15:34:40 -07:00 |
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James E. Stine
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eb64a7f0c9
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Update to fpdivsqrt to go on posedge as it should. Also an update to
individual regression test for TestFloat (still needs some tweaking)
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2021-10-13 17:14:42 -05:00 |
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Katherine Parry
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09f51871c5
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lint warnings fixed
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2021-10-12 09:45:02 -07:00 |
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Katherine Parry
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4ea56ac68b
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some fpu lint warnings fixed - still working on it
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2021-10-11 18:32:03 -07:00 |
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Shreya Sanghai
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51185478df
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made redunantmul generate DW02_multp for synopsys sythnesis
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2021-10-11 11:54:39 -07:00 |
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Shreya Sanghai
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295a3c7af2
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actually added redundant mul
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2021-10-11 11:29:13 -07:00 |
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Shreya Sanghai
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324230e2f9
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added redundant multiplier
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2021-10-11 11:20:12 -07:00 |
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David Harris
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fc39f77cba
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Starting to optimize multiplier
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2021-10-11 11:06:07 -07:00 |
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David Harris
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8a64675b02
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intdiv cleanup
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2021-10-11 08:14:21 -07:00 |
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David Harris
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a8ce4568aa
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Divider FSM simplification
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2021-10-10 22:24:14 -07:00 |
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David Harris
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a077735ecc
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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David Harris
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266c706804
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-10 12:26:15 -07:00 |
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David Harris
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77f1ae54d8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-10 12:25:11 -07:00 |
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bbracker
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8eff03bf1a
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simplify flopenrc's that didn't actually need to be flopenrc's
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2021-10-10 12:25:05 -07:00 |
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David Harris
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93e6ec96a7
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Divider cleanup
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2021-10-10 12:24:44 -07:00 |
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David Harris
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6d2d93deeb
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Simplifying divider FSM
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2021-10-10 12:21:43 -07:00 |
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David Harris
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2d09994a91
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Simplifying divider FSM
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2021-10-10 12:21:36 -07:00 |
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David Harris
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644af40855
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Moved & ~StallM from FSM into DivStartE
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2021-10-10 11:49:32 -07:00 |
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David Harris
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e93014d6d8
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Moved divide iteration register names to M stage
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2021-10-10 11:30:53 -07:00 |
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David Harris
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e8d013b106
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Simplified remainder for divide by 0
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2021-10-10 11:20:07 -07:00 |
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David Harris
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94fd682cdc
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divider control signal simplificaiton
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2021-10-10 10:55:02 -07:00 |
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David Harris
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bfe8bf3855
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Removed negedge flops from divider
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2021-10-10 10:41:13 -07:00 |
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David Harris
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99fd79c20b
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Simplified divider sign handling
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2021-10-10 08:35:26 -07:00 |
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David Harris
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eaa8be14b9
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renamed DivStart
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2021-10-10 08:32:04 -07:00 |
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David Harris
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5cb30164d4
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renamed DivSigned
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2021-10-10 08:30:19 -07:00 |
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Katherine Parry
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44b023ace1
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FMA matches diagram and lint warnings fixed
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2021-10-09 17:38:10 -07:00 |
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kipmacsaigoren
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086e6d130a
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rename adder in fpu for synthesis
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2021-10-08 17:47:54 -05:00 |
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kipmacsaigoren
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8e35701103
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Merging new changes into the old one's I've made in the OKstate servers
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2021-10-08 17:47:11 -05:00 |
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Kip Macsai-Goren
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3623dfa51e
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removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.
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2021-10-08 15:33:18 -07:00 |
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kipmacsaigoren
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3103b78493
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-08 12:01:44 -05:00 |
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bbracker
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25e0745a6a
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fix div restarting bug
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2021-10-07 18:55:00 -04:00 |
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kipmacsaigoren
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086a0234ba
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-06 11:52:34 -05:00 |
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James E. Stine
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b90d7b8083
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Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
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2021-10-06 08:26:09 -05:00 |
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