196 Commits

Author	SHA1	Message	Date
Jarred Allen	307e33bc7e	Remove DelaySideD since it isn't needed	2021-03-22 15:13:23 -04:00
Jarred Allen	99fa8beef3	Update icache interface	2021-03-22 15:04:46 -04:00
Jarred Allen	2269879459	Merge branch 'main' into cache	2021-03-22 13:47:48 -04:00
bbracker	eea7e2e47e	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Katherine Parry	9af0ad815c	fixed various bugs in the FMA	2021-03-21 22:53:04 +00:00
Jarred Allen	066dc2caac	Fix bug with PC incrementing	2021-03-20 18:06:03 -04:00
Jarred Allen	e531a1b5ee	Merge branch 'main' into cache	2021-03-20 17:56:25 -04:00
Jarred Allen	665c244ba1	Fix another bug in the icache (why so many of them?)	2021-03-20 17:54:40 -04:00
Jarred Allen	43a8cb0354	Revert "Change flop to listen to StallF" ... This reverts commit f069b759be.	2021-03-20 17:34:19 -04:00
Jarred Allen	f069b759be	Change flop to listen to StallF	2021-03-20 17:04:13 -04:00
Katherine Parry	fd381e60d7	messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic	2021-03-20 02:05:16 +00:00
Jarred Allen	50c961bbe4	Merge changes from main	2021-03-18 18:58:10 -04:00
bbracker	df51d9908d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
bbracker	11ba96f2e3	maybe AHB works now	2021-03-18 17:47:00 -04:00
Shreya Sanghai	dfc86539cc	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	9386e6a524	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00
Ross Thompson	181a28e875	Fixed minor bug with the size of gshare.	2021-03-18 16:00:09 -05:00
Shreya Sanghai	f35d3b39c8	removed unnecesary PC registers in ifu	2021-03-18 16:31:21 -04:00
Thomas Fleming	859d242d81	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-18 14:36:42 -04:00
Thomas Fleming	062c4d40da	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
Noah Boorstin	847bf0b9a6	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	fa1407f6e3	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Shreya Sanghai	d9b1e7d67f	added gshare and global history predictor	2021-03-16 17:03:01 -04:00
Jarred Allen	3fc36b978d	Fix icache for jumping into misaligned instructions	2021-03-16 16:57:51 -04:00
Shreya Sanghai	a79e26f9d8	added global history branch predictor	2021-03-16 16:06:40 -04:00
Jarred Allen	98db312574	Merge remote-tracking branch 'origin/main' into cache	2021-03-16 14:17:39 -04:00
Shreya Sanghai	23a7c8cd92	made performance counters count branch misprediction	2021-03-16 11:24:17 -04:00
Shreya Sanghai	518618ad38	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Jarred Allen	5b174adc2a	Fix BEQZ tests	2021-03-14 15:42:27 -04:00
Jarred Allen	003242ae8a	Merge upstream changes	2021-03-14 14:57:53 -04:00
Jarred Allen	c2f2caa3f6	Get non-jump case working	2021-03-14 14:46:21 -04:00
bbracker	b30ea396b8	slightly smarter dtim HREADY	2021-03-13 07:03:33 -05:00
bbracker	63bfd79009	slightly smarter dtim HREADY	2021-03-13 06:55:34 -05:00
bbracker	12721837f0	imem rd2 adrbits bugfix	2021-03-13 00:10:41 -05:00
bbracker	0f49108ee6	clint HREADY signal update	2021-03-12 20:23:55 -05:00
Ross Thompson	ccaaa829ce	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-12 14:58:04 -06:00
Ross Thompson	0637874cac	Cleanup of the branch predictor flush and stall controls.	2021-03-12 14:57:53 -06:00
David Harris	d4e84c58ed	64-bit AMO debugged	2021-03-11 23:18:33 -05:00
Thomas Fleming	e57b6cf18c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
David Harris	fe4d288589	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
Noah Boorstin	2d1f63b590	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
Jarred Allen	c0ee17b6ac	Merge upstream changes	2021-03-09 21:20:34 -05:00
Jarred Allen	81b29a3891	More progress	2021-03-09 21:16:07 -05:00
David Harris	bea8ac6d59	WALLY-LRSC atomic test passing	2021-03-09 09:28:25 -05:00
David Harris	52d4a04eb0	Created atomic test vector and directories	2021-03-08 09:38:55 -05:00
Ross Thompson	d6bc34121f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-05 15:27:22 -06:00
Ross Thompson	9a93193d6a	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Thomas Fleming	ca2a65770c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-05 15:46:51 -05:00
Noah Boorstin	f0a103687e	Merge branch 'main' into busybear	2021-03-05 20:27:19 +00:00
bbracker	612f7a9ee4	added a delay to sel signals	2021-03-05 15:07:34 -05:00