slmnemo
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6c237e43d8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-19 17:51:45 -07:00 |
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slmnemo
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a5490c7096
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Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace
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2022-05-19 17:51:26 -07:00 |
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slmnemo
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05d14bdb3c
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Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py
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2022-05-19 17:50:48 -07:00 |
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slmnemo
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0982417054
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Fixed buildroot by adding a second .
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2022-05-19 17:49:32 -07:00 |
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slmnemo
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7d2bfb6db8
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parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do
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2022-05-19 16:21:38 -07:00 |
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Katherine Parry
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bc4804d90a
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fixed lint warning
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2022-05-19 20:34:06 +00:00 |
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Katherine Parry
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b0881495a9
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Bug fixed in unpacker and sub/add/mul tests pass TestFloat
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2022-05-19 20:31:23 +00:00 |
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mmasserfrye
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b255f61521
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-19 20:24:57 +00:00 |
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mmasserfrye
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710905b239
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updated synth plotting and regression
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2022-05-19 20:24:47 +00:00 |
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Katherine Parry
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cc0ab94ebc
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Added fp tests - doesnpass yet
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2022-05-19 16:32:30 +00:00 |
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slmnemo
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af14c8a064
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added instructions to slack notifier
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2022-05-18 16:50:31 -07:00 |
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mmasserfrye
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1442afe4e2
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added support for plotting and fitting power
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2022-05-18 17:01:55 +00:00 |
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mmasserfrye
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1888a9a665
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-18 16:10:36 +00:00 |
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mmasserfrye
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0265d1988e
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adapted shifter in ppa.sv for widths beside 32 and 64
modified plotting and regression in ppaAnalyze.py
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2022-05-18 16:08:40 +00:00 |
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Ross Thompson
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9079e67aae
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Updated fpga debugger.
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2022-05-17 23:04:01 -05:00 |
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slmnemo
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7cd673fa6e
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simplified make-tests.sh to run the current makefile in regression
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2022-05-17 17:29:34 -07:00 |
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slmnemo
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ebeebf3bfc
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Revert "same as last breaking commit, testing if the bisect works to output a breaking commit."
This reverts commit 910475ea56.
gottem
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2022-05-17 17:26:33 -07:00 |
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slmnemo
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910475ea56
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same as last breaking commit, testing if the bisect works to output a breaking commit.
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2022-05-17 17:22:09 -07:00 |
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slmnemo
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36ea0f9126
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Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D."
This reverts commit 0dea11fc73.
fixed it
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2022-05-17 17:05:11 -07:00 |
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slmnemo
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0dea11fc73
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broke it again but this time it doesn't compile due to a missing semicolon on Rs1D.
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2022-05-17 17:03:16 -07:00 |
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slmnemo
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73d19b0956
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Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression"
This reverts commit 83e4ab711c.
unbroke wally
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2022-05-17 16:57:29 -07:00 |
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slmnemo
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29bc8d6902
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Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main""
This reverts commit c15aab9c6f.
reverted the wrong commit
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2022-05-17 16:57:00 -07:00 |
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slmnemo
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c15aab9c6f
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Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main"
This reverts commit d601c89d2a, reversing
changes made to 1131d41343.
undid things
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2022-05-17 16:54:29 -07:00 |
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slmnemo
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83e4ab711c
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Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression
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2022-05-17 16:33:09 -07:00 |
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slmnemo
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d601c89d2a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Added empty directory '/wkdir' to /pipelined/regression to avoid tests failing out of box due to the missing directory
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2022-05-17 20:32:53 +00:00 |
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slmnemo
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1131d41343
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added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
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2022-05-17 20:32:38 +00:00 |
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David Harris
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83494e349b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-17 15:09:52 +00:00 |
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David Harris
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20c861ee6f
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Restored srt to working without exponent unit
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2022-05-17 15:09:48 +00:00 |
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mmasserfrye
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43cf4f35cd
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-17 01:11:58 +00:00 |
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mmasserfrye
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24420dea6c
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added 8 and 128 bit versions, adjusted alu
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2022-05-17 01:11:43 +00:00 |
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slmnemo
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ba572b46f4
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Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.
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2022-05-17 01:04:13 +00:00 |
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slmnemo
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ede0a3237d
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quit
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2022-05-17 01:03:09 +00:00 |
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David Harris
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0fb6fe4cc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-17 00:07:09 +00:00 |
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David Harris
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b992a61ca3
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removed exptestgen
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2022-05-17 00:06:44 +00:00 |
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David Harris
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7aba83a35c
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Cleaned up unpacker changes in srt and lint errors
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2022-05-17 00:06:14 +00:00 |
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slmnemo
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c84731d6d0
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Fixed grammar on two comments in bpred.sv
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2022-05-16 22:41:18 +00:00 |
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mmasserfrye
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c8e43e9798
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
resolved merge conflict
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2022-05-16 15:42:59 +00:00 |
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mmasserfrye
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2ca897620f
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tuning modules for ppa
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2022-05-16 15:39:15 +00:00 |
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David Harris
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f5e2cff45a
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Cause simplification
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2022-05-12 23:47:21 +00:00 |
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David Harris
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6303d4e81f
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Cause simplification
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2022-05-12 23:39:10 +00:00 |
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David Harris
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c4621c5b6b
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Cause simplification
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2022-05-12 23:37:40 +00:00 |
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David Harris
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7daf631c13
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Cause simplification
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2022-05-12 23:33:35 +00:00 |
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David Harris
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de51c7eeb3
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Cause simplification
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2022-05-12 23:33:22 +00:00 |
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David Harris
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803bfc4fe4
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Cause simplification
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2022-05-12 23:29:35 +00:00 |
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David Harris
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2d27d20db9
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Cause simplification
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2022-05-12 23:27:02 +00:00 |
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David Harris
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87dadc8208
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trap/csr cleanup
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2022-05-12 22:26:21 +00:00 |
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David Harris
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ea0d9fd9a8
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More trap/csr simplification
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2022-05-12 22:06:03 +00:00 |
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David Harris
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2eb6a65fa2
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More trap/csr simplification
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2022-05-12 22:04:20 +00:00 |
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David Harris
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2d8ccbd4ea
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More trap/csr simplification
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2022-05-12 22:00:23 +00:00 |
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David Harris
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417e36bff5
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More trap/csr simplification
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2022-05-12 21:55:50 +00:00 |
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David Harris
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ca6b7716e2
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Simplifying trap/csr interface
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2022-05-12 21:50:15 +00:00 |
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David Harris
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56c154f2e7
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Simplified MTVAL logic
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2022-05-12 21:36:13 +00:00 |
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David Harris
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730bcac6ba
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Partitioned privileged pipeline registers into module
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2022-05-12 20:45:45 +00:00 |
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David Harris
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c5868b81e4
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privileged cleanup
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2022-05-12 20:21:33 +00:00 |
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mmasserfrye
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517e44746e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-12 20:20:40 +00:00 |
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mmasserfrye
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2675c217e0
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cleaned lint for ppa.sv
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2022-05-12 20:20:05 +00:00 |
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David Harris
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5537c33196
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Formatting cleanup
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2022-05-12 18:37:47 +00:00 |
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mmasserfrye
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57a69d0f67
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-12 18:08:20 +00:00 |
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mmasserfrye
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30a1ba7bcf
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renamed madzscript, modified ppa.sv alu and shifter
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2022-05-12 18:05:02 +00:00 |
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David Harris
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449472ba58
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Moved Breakpoint and Ecall fault logic into privdec
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2022-05-12 16:45:53 +00:00 |
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David Harris
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9f8dca5190
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Moved TLB Flush logic into privdec
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2022-05-12 16:41:52 +00:00 |
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David Harris
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1d01bc98a4
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Moved WFI timeout into privdec
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2022-05-12 16:22:39 +00:00 |
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David Harris
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21c1e58829
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Partitioned privilege mode fsm into new module
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2022-05-12 16:16:42 +00:00 |
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David Harris
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61199ccd13
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More signal cleanup
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2022-05-12 15:39:44 +00:00 |
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David Harris
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4c5e361b00
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More unused signal cleanup
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2022-05-12 15:26:08 +00:00 |
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David Harris
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5acb526375
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More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
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David Harris
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7e764fbda1
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More unused signal cleanup
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2022-05-12 15:15:30 +00:00 |
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David Harris
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e2dea3bb89
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Removed more unused signals, simplified csri state
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2022-05-12 15:10:10 +00:00 |
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David Harris
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fb725a9e0a
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Clean up unused signals
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2022-05-12 14:49:58 +00:00 |
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David Harris
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8372bc86a7
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Removing unused signals
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2022-05-12 14:36:15 +00:00 |
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David Harris
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15659b05e4
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Simplifed mstatus.TSR handling
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2022-05-12 14:09:52 +00:00 |
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David Harris
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877c4eefd1
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Fixed typo in csrm
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2022-05-12 06:55:39 -07:00 |
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mmasserfrye
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cf900cf44d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-12 07:24:04 +00:00 |
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mmasserfrye
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52b0e7d567
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filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv
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2022-05-12 07:22:06 +00:00 |
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David Harris
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32f8841f79
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Added MCONFIGPTR CSR hardwired to 0
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2022-05-12 04:31:45 +00:00 |
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David Harris
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c738c130de
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merged ppa.sv
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2022-05-11 18:14:16 +00:00 |
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David Harris
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e37d262e4c
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PPA script progress
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2022-05-11 18:11:51 +00:00 |
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mmasserfrye
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70fe1184db
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ed
modified ppa.sv
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2022-05-11 16:22:12 +00:00 |
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David Harris
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a8c9f504fa
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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91472eb948
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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91b786c58d
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Updated PPA experiment
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2022-05-10 23:09:42 +00:00 |
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David Harris
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d53e4b1b1f
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Initial PPA study
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2022-05-10 20:48:47 +00:00 |
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David Harris
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b869190161
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endian swapper
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2022-05-08 06:51:50 +00:00 |
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David Harris
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8066ba45e8
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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David Harris
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2792d77e4e
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Fixed bug in delegated interrupts not being taken
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2022-05-08 04:50:27 +00:00 |
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David Harris
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2cdd49c7d2
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WFI terminates when an interrupt is pending even if interrupts are globally disabled
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2022-05-08 04:30:46 +00:00 |
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David Harris
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7024293a59
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Zero'd wfiM when ZICSR not supported to fix hang in E tests
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2022-05-05 15:32:13 +00:00 |
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David Harris
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66424a8246
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SFENCE.VMA should be illegal in user mode
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2022-05-05 15:15:02 +00:00 |
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David Harris
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866540580a
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SFENCE.VMA should be illegal in user mode
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2022-05-05 14:59:52 +00:00 |
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David Harris
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c100c9893b
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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David Harris
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94459ade3d
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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25ad39939f
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put privileged tests back into rv32/64gc
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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0f70e48b6b
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updated makefrag and tests.vh to reflect removed tests, new names
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2022-05-04 21:20:25 +00:00 |
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David Harris
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8eee0c0ca3
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-03 18:32:04 +00:00 |
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David Harris
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554c2b3550
|
Illegal instruction fault when running FPU instruction with STATUS_FS = 0
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2022-05-03 18:32:01 +00:00 |
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David Harris
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cb1a7d54a4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-03 08:53:35 -07:00 |
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David Harris
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4fbf78e049
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clean up sram1p1rw; still doesn't work on Modelsim 2022.1
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2022-05-03 08:31:54 -07:00 |
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David Harris
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9c4de0e9c1
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
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David Harris
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dee32f70bf
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Switched to behavioral comparator for best PPA
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2022-05-03 11:00:39 +00:00 |
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David Harris
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bc123b5564
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Comparator experiments
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2022-05-03 10:54:30 +00:00 |
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