44 Commits

Author	SHA1	Message	Date
Ross Thompson	cec50ce208	The valid and dirty bits match the SRAM implementation now.	2022-09-22 16:09:09 -05:00
Ross Thompson	b48d6b5e1f	Solved the sram write first / read first issue. Works correctly with read first now.	2022-09-22 14:16:26 -05:00
Ross Thompson	ac864a6ca3	Merged together bram1p1rw with sram1p1rw as sram1p1rw. ... Fixed a major issue with the real SRAM implemenation.	2022-09-21 12:20:00 -05:00
Ross Thompson	57fcf0ef79	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Ross Thompson	a79e5e11f6	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
Ross Thompson	0ef6137ab9	Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.	2022-07-17 21:05:31 -05:00
Ross Thompson	8356e5d742	Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.	2022-07-17 16:20:04 -05:00
Katherine Parry	18d7fee541	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-12 22:37:20 +00:00
David Harris	d1a7832dd9	added comment about RAMs in cacheway	2022-07-10 12:47:34 +00:00
Katherine Parry	62205ebb3b	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
David Harris	38ef8eebbb	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
Katherine Parry	8f98f3bfab	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	83133f8c47	Partially working byte write enables. Works for cache, but not dtim or bus only.	2022-03-10 16:11:39 -06:00
Ross Thompson	d5f524a15e	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
Ross Thompson	6e1a0af5d0	Eliminated more ports in cacheway.	2022-02-13 15:53:46 -06:00
Ross Thompson	a440bc2ac5	More cache cleanup.	2022-02-13 15:47:27 -06:00
Ross Thompson	f87a6f2c63	More cache cleanup.	2022-02-13 12:38:39 -06:00
Ross Thompson	f5c4bca47e	Formating improvements to cache.	2022-02-11 23:10:58 -06:00
Ross Thompson	411997010b	Replacement policy cleanup.	2022-02-10 11:40:10 -06:00
Ross Thompson	fc68c2f09a	Cache name clarifications.	2022-02-10 10:50:17 -06:00
Ross Thompson	e00d404154	More cache cleanup.	2022-02-10 10:43:37 -06:00
Ross Thompson	65803ebe98	structural muxes.	2022-02-09 19:36:21 -06:00
Ross Thompson	01126535db	Annotated the final changes required to move sram address off the critial path.	2022-02-08 18:17:31 -06:00
Ross Thompson	498388c636	Cache cleanup write enables.	2022-02-08 17:52:09 -06:00
Ross Thompson	492c1473f3	Preparing to make a major change to the cache's write enables.	2022-02-08 09:47:01 -06:00
Ross Thompson	ca459a5915	Removed VDWriteEnable.	2022-02-07 21:59:18 -06:00
Ross Thompson	23a60d9875	Progress towards simplifying the cache's write enables.	2022-02-07 17:23:09 -06:00
Ross Thompson	498c2b589a	Optimization of cache save/restore.	2022-02-04 14:21:04 -06:00
Ross Thompson	83fdedcec6	Working first cut of the cache changes moving the replay to a save/restore. ... The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.	2022-02-04 13:31:32 -06:00
David Harris	0e1d784b60	sram1rw cleanup	2022-02-03 17:50:23 +00:00
David Harris	9b6a4d1d52	cacheway cleanup	2022-02-03 16:52:22 +00:00
David Harris	7a8cc5ef21	cacheway cleanup	2022-02-03 16:33:01 +00:00
David Harris	0fbc32204c	cacheway cleanup	2022-02-03 16:07:55 +00:00
David Harris	c22f7eb11c	cacheway cleanup	2022-02-03 16:00:57 +00:00
David Harris	e92461159d	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
Ross Thompson	f604a0d79e	cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.	2022-01-05 22:56:18 -06:00
Ross Thompson	da585b30f9	Slower but correct implementation of flush.	2022-01-05 16:57:22 -06:00
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00