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183 lines
8.5 KiB
Systemverilog
183 lines
8.5 KiB
Systemverilog
///////////////////////////////////////////
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// cacheway
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//
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// Written: ross1728@gmail.com July 07, 2021
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// Implements the data, tag, valid, dirty, and replacement bits.
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (
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input logic clk,
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input logic reset,
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input logic [$clog2(NUMLINES)-1:0] RAdr,
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input logic [`PA_BITS-1:0] PAdr,
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input logic [LINELEN-1:0] CacheWriteData,
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input logic FStore2,
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input logic SetValidWay,
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input logic ClearValidWay,
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input logic SetDirtyWay,
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input logic ClearDirtyWay,
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input logic SelEvict,
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input logic SelFlush,
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input logic VictimWay,
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input logic FlushWay,
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input logic Invalidate,
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input logic [(`XLEN-1)/8:0] ByteMask,
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output logic [LINELEN-1:0] ReadDataLineWay,
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output logic HitWay,
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output logic VictimDirtyWay,
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output logic [TAGLEN-1:0] VictimTagWay);
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localparam integer WORDSPERLINE = LINELEN/`XLEN;
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localparam integer BYTESPERLINE = LINELEN/8;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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localparam LOGXLENBYTES = $clog2(`XLEN/8);
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localparam integer BYTESPERWORD = `XLEN/8;
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logic [NUMLINES-1:0] ValidBits;
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logic [NUMLINES-1:0] DirtyBits;
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logic [LINELEN-1:0] ReadDataLine;
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logic [TAGLEN-1:0] ReadTag;
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logic Valid;
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logic Dirty;
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logic SelData;
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logic SelTag;
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logic [$clog2(NUMLINES)-1:0] RAdrD;
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logic [2**LOGWPL-1:0] MemPAdrDecoded;
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logic [WORDSPERLINE-1:0] SelectedWriteWordEn;
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logic [(`XLEN-1)/8:0] FinalByteMask;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Enable demux
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`LLEN>`XLEN)begin
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logic [2**LOGWPL-1:0] MemPAdrDecodedtmp;
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onehotdecoder #(LOGWPL) adrdec(
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.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedtmp));
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assign MemPAdrDecoded = MemPAdrDecodedtmp|{MemPAdrDecodedtmp[2**LOGWPL-2:0]&{2**LOGWPL-1{FStore2}}, 1'b0};
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end else
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onehotdecoder #(LOGWPL) adrdec(
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.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
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// If writing the whole line set all write enables to 1, else only set the correct word.
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assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND
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assign FinalByteMask = SetValidWay ? '1 : ByteMask; // OR
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Tag Array
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/////////////////////////////////////////////////////////////////////////////////////////////
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk,
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.Adr(RAdr), .ReadData(ReadTag), .ByteMask('1),
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.CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay));
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// AND portion of distributed tag multiplexer
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mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
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assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux
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assign VictimDirtyWay = SelTag & Dirty & Valid;
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assign HitWay = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Data Array
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/////////////////////////////////////////////////////////////////////////////////////////////
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// *** instantiate one larger RAM, not one per RAM. Expand byte mask
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genvar words;
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logic [BYTESPERLINE-1:0] ReplicatedByteMask, SRAMLineByteMask, WordByteEnabled;
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assign ReplicatedByteMask = {{WORDSPERLINE}{FinalByteMask}};
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for(words = 0; words < WORDSPERLINE; words++)
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assign WordByteEnabled[BYTESPERWORD*(words+1)-1:BYTESPERWORD*(words)] = {{BYTESPERWORD}{SelectedWriteWordEn[words]}};
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assign SRAMLineByteMask = ReplicatedByteMask & WordByteEnabled;
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localparam integer SRAMLEN = 256;
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localparam integer NUMSRAM = LINELEN/SRAMLEN;
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localparam integer SRAMLENINBYTES = SRAMLEN/8;
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localparam integer LOGNUMSRAM = $clog2(NUMSRAM);
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for(words = 0; words < NUMSRAM; words++) begin: word
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .Adr(RAdr),
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.ReadData(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.CacheWriteData(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.WriteEnable(1'b1), .ByteMask(SRAMLineByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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end
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/* -----\/----- EXCLUDED -----\/-----
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for(words = 0; words < 1; words++) begin: word
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(LINELEN)) CacheDataMem(.clk, .Adr(RAdr),
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.ReadData(ReadDataLine),
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.CacheWriteData(CacheWriteData),
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.WriteEnable(1'b1), .ByteMask(SRAMLineByteMask));
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end
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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for(words = 0; words < WORDSPERLINE; words++) begin: word
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr),
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.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
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.CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]),
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.WriteEnable(SelectedWriteWordEn[words]), .ByteMask(FinalByteMask));
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end
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-----/\----- EXCLUDED -----/\----- */
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// AND portion of distributed read multiplexers
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mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);
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assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux.
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Valid Bits
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/////////////////////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk) begin // Valid bit array,
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if (reset | Invalidate) ValidBits <= #1 '0;
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else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1;
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else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0;
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end
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flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
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assign Valid = ValidBits[RAdrD];
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Dirty Bits
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Dirty bits
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if (DIRTY_BITS) begin:dirty
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always_ff @(posedge clk) begin
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if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1;
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else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0;
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end
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assign Dirty = DirtyBits[RAdrD];
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end else assign Dirty = 1'b0;
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endmodule
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