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https://github.com/openhwgroup/cvw
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137 lines
6.1 KiB
Systemverilog
137 lines
6.1 KiB
Systemverilog
///////////////////////////////////////////
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// cacheway
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//
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// Written: ross1728@gmail.com July 07, 2021
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// Implements the data, tag, valid, dirty, and replacement bits.
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (
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input logic clk,
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input logic reset,
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input logic [$clog2(NUMLINES)-1:0] RAdr,
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input logic [`PA_BITS-1:0] PAdr,
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input logic WriteEnable,
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input logic [LINELEN/`XLEN-1:0] WriteWordEnable,
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input logic TagWriteEnable,
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input logic [LINELEN-1:0] WriteData,
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input logic SetValid,
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input logic ClearValid,
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input logic SetDirty,
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input logic ClearDirty,
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input logic SelEvict,
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input logic Victim,
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input logic InvalidateAll,
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input logic SelFlush,
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input logic Flush,
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output logic [LINELEN-1:0] SelectedReadDataLine,
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output logic WayHit,
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output logic VictimDirty,
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output logic [TAGLEN-1:0] VictimTag);
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logic [NUMLINES-1:0] ValidBits;
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logic [NUMLINES-1:0] DirtyBits;
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logic [LINELEN-1:0] ReadDataLine;
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logic [TAGLEN-1:0] ReadTag;
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logic Valid;
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logic Dirty;
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logic SelData;
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logic SelTag;
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logic [$clog2(NUMLINES)-1:0] RAdrD;
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logic SetValidD, ClearValidD;
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logic SetDirtyD, ClearDirtyD;
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logic WriteEnableD;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Tag Array
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/////////////////////////////////////////////////////////////////////////////////////////////
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sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk),
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.Adr(RAdr), .ReadData(ReadTag),
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.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable));
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// AND portion of distributed tag multiplexer
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assign SelTag = SelFlush ? Flush : Victim;
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assign VictimTag = SelTag ? ReadTag : '0; // AND part of AOMux
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assign VictimDirty = SelTag & Dirty & Valid;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Data Array
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/////////////////////////////////////////////////////////////////////////////////////////////
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// *** Potential optimization: if byte write enables are available, could remove subwordwrites
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genvar words;
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for(words = 0; words < LINELEN/`XLEN; words++) begin: word
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sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr),
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.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
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.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
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.WriteEnable(WriteEnable & WriteWordEnable[words]));
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end
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// AND portion of distributed read multiplexers
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assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
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assign SelData = SelFlush ? Flush : (SelEvict ? Victim : WayHit);
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assign SelectedReadDataLine = SelData ? ReadDataLine : '0; // AND part of AO mux.
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Valid Bits
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/////////////////////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk) begin // Valid bit array,
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if (reset | InvalidateAll) ValidBits <= #1 '0;
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else if (SetValidD) ValidBits[RAdrD] <= #1 1'b1;
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else if (ClearValidD) ValidBits[RAdrD] <= #1 1'b0;
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end
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// *** consider revisiting whether these delays are the best option?
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flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
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flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable},
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{SetValidD, ClearValidD, WriteEnableD});
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assign Valid = ValidBits[RAdrD];
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Dirty Bits
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Dirty bits
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if (DIRTY_BITS) begin:dirty
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always_ff @(posedge clk) begin
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if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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else if (SetDirtyD) DirtyBits[RAdrD] <= #1 1'b1;
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else if (ClearDirtyD) DirtyBits[RAdrD] <= #1 1'b0;
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end
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flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
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assign Dirty = DirtyBits[RAdrD];
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end else assign Dirty = 1'b0;
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endmodule
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