Ross Thompson
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7099259ff7
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I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
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2022-03-25 13:10:31 -05:00 |
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bbracker
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9f60256f22
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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6ab14d7302
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Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
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2022-03-22 22:04:06 -05:00 |
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bbracker
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be2f668867
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but apparently QEMU doesn't show UXL in SSTATUS
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2022-03-02 22:44:19 +00:00 |
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bbracker
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01e0f2f0d2
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update SXL UXL bits in MSTATUS to match new QEMU trace
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2022-03-02 22:15:57 +00:00 |
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David Harris
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c23db6a31e
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Cleaned warning on HPTW default state
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2022-02-16 17:40:13 +00:00 |
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David Harris
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aa990be959
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removed csrn and all of its outputs because depricated
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2022-02-15 19:59:29 +00:00 |
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David Harris
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d8170e9dd3
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Mostly removed N_SUPPORTED
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2022-02-15 19:50:44 +00:00 |
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David Harris
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ed8ac3d881
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Just needed to recompile - all good. Now removed uretM because N-mode is depricated
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2022-02-15 19:48:49 +00:00 |
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David Harris
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5ef8f6bc7e
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Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
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2022-02-15 19:20:41 +00:00 |
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David Harris
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9e0055cbb9
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More config file cleanup; 32ic tests broken
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2022-02-03 01:08:34 +00:00 |
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David Harris
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c12407ba6a
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Removed Busybear dependencies
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2022-02-02 20:28:21 +00:00 |
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Ross Thompson
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1476a79ea2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-31 12:17:37 -06:00 |
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David Harris
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2d112698b7
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Replaced || and && with | and &
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2022-01-31 01:07:35 +00:00 |
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Ross Thompson
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7fedc6b878
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Cleaned up the InstrMisalignedFault.
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2022-01-28 13:19:24 -06:00 |
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Ross Thompson
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1bb8d36308
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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Ross Thompson
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ec44774c77
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Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
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2022-01-20 16:39:54 -06:00 |
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Ross Thompson
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5cf686429d
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Merged in the debug ila updates.
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2022-01-18 17:29:21 -06:00 |
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Ross Thompson
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fdc17f5017
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Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
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2022-01-18 17:19:33 -06:00 |
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Ross Thompson
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000d713cb5
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Better solution to the integer divider interrupt interaction.
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2022-01-12 14:22:18 -06:00 |
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Ross Thompson
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48c036a923
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Oups. My hack for DivE interrupt prevention was wrong.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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796316495d
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Hack "fix" to prevent interrupt from occuring during an integer divide.
This is not the desired solution but will allow continued debuging of linux.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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55456e465c
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Added icache access and icache miss to performance counters.
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2022-01-09 22:56:56 -06:00 |
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David Harris
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3d2671a8b0
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Reformatted MIT license to 95 characters
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2022-01-07 12:58:40 +00:00 |
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David Harris
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d66f7c841b
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Removed generate statements
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2022-01-05 14:35:25 +00:00 |
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David Harris
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115287adc8
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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