Rose Thompson
2e4ca4c876
Merge pull request #895 from davidharrishmc/dev
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Fix Issue 894 about floating-point decoding of reserved rm/frm
2024-07-25 11:51:32 -05:00
David Harris
7360be1234
Legalized PMPconfig WARL
2024-07-25 09:43:54 -07:00
David Harris
c637e40058
CHeck legal rnum field when decoding aes64ks1i
2024-07-25 09:19:23 -07:00
David Harris
7234abebef
Issue #894 : trap on floating-point ops with reserved rounding modes: detect Zfa flt
2024-07-25 09:09:13 -07:00
David Harris
337e40ac1b
Issue #894 : trap on floating-point ops with reserved rounding modes
2024-07-25 06:59:58 -07:00
David Harris
5ac02c79c6
Merge pull request #892 from ross144/main
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Adds synthesizable RVVI FPGA hardware
2024-07-24 12:21:36 -07:00
Rose Thompson
5a6e32576d
Fixed the reset bug in wallyTracer.
2024-07-24 13:32:46 -05:00
Rose Thompson
994386f12c
Removed unused file.
2024-07-24 13:30:25 -05:00
Rose Thompson
9053923d92
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-24 13:14:25 -05:00
Rose Thompson
13db14db6b
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
c11036358a
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
fb1869fcb9
Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
2024-07-24 10:13:03 -05:00
Rose Thompson
7960f26e84
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
2024-07-23 17:44:37 -05:00
Rose Thompson
35efbd6a54
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
bfb3b63a24
Code cleanup.
2024-07-23 16:35:05 -05:00
Rose Thompson
fe9ac36928
Fixed rvvi csr counting.
2024-07-23 16:22:23 -05:00
Rose Thompson
da2511c63c
Fixed bugs in the rvvi synth logic which encoded csr instructions.
2024-07-23 16:16:11 -05:00
Rose Thompson
7bc04702a7
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
2024-07-23 13:18:03 -05:00
Rose Thompson
f20b82b14e
Moved all rvvi files to rvvi directory.
2024-07-23 13:03:21 -05:00
Rose Thompson
d706b5b898
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
2024-07-23 12:26:03 -05:00
Rose Thompson
b30656447f
Resolved more lint errors in the rvvi synthesized hardware.
2024-07-23 12:23:04 -05:00
Rose Thompson
ebd8082508
Merge pull request #891 from davidharrishmc/dev
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Increased covergen.py functional coverage to 87.6%
2024-07-23 09:34:13 -05:00
David Harris
b7fb786749
Increased covergen.py functional coverage to 87.6%
2024-07-23 04:38:13 -07:00
Rose Thompson
c6c2240630
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 17:48:34 -05:00
Rose Thompson
5381e1f395
Updated for a better ILA rvvi debugger.
2024-07-22 17:44:04 -05:00
Rose Thompson
3c06556833
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
2024-07-22 16:12:06 -05:00
Rose Thompson
35e69944fa
Cleaned up rvvisynth.sv
2024-07-22 12:22:41 -05:00
Rose Thompson
efa99940c5
Added option to use rvvi ila
2024-07-22 12:19:37 -05:00
Rose Thompson
02f108345a
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
4695e25a4c
Merge pull request #890 from davidharrishmc/dev
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Fixed argument name in regression-wally
2024-07-22 12:00:25 -05:00
David Harris
db2614f573
Fixed argument name in regression-wally
2024-07-22 09:19:56 -07:00
Rose Thompson
8f1450c3db
Merge pull request #889 from davidharrishmc/dev
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Functional coverage improvements, fix WARL bug on MTVEC/STVEC
2024-07-22 10:59:16 -05:00
David Harris
a9fd6e6cfb
Added more RV64I coverage generation
2024-07-22 08:52:19 -07:00
Rose Thompson
24609f0b7f
Now have configurations to switch between supporting RVVI over ethernet.
2024-07-22 10:51:13 -05:00
David Harris
bf9442c5a5
Added QuestaFunctCoverage to merge functional coverage reports
2024-07-22 08:49:54 -07:00
David Harris
13f1aa1ebf
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
Rose Thompson
a8f293c61a
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 10:01:33 -05:00
David Harris
0781a32991
Removed more obsolete imperas scripts
2024-07-21 19:47:23 -07:00
David Harris
d6be3bdc4e
Fixed makefile log typo
2024-07-21 19:47:00 -07:00
David Harris
6ca7845c93
Fixed hazard and rd_maxval coverage generation
2024-07-21 19:46:30 -07:00
David Harris
e8caf1717d
Removed outdated wally-imperas files
2024-07-21 19:45:22 -07:00
Jordan Carlin
4859f73ef0
Merge pull request #888 from davidharrishmc/dev
2024-07-21 12:04:29 -07:00
David Harris
f5f8a6c50c
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
ce2cc48642
Updated verilog-ethernet to be compatible with wally.
2024-07-19 13:36:26 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
Rose Thompson
9c1779a2d5
Added some documenation about sparse-checkout for verilog-ethernet submodule.
2024-07-19 13:11:48 -05:00
Rose Thompson
6aaa77dae0
Merge pull request #887 from davidharrishmc/dev
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Fully decode decompressed instructions, including hints and illegal registers/immediates
2024-07-19 09:23:36 -05:00
