Thomas Fleming
2e2eb5839f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 13:35:44 -05:00
Thomas Fleming
8c97143be6
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Thomas Fleming
7e11317a2d
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Ross Thompson
a662aa487c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-04 17:31:27 -06:00
Katherine Parry
cfac6bf0c7
fixed various bugs
2021-03-04 22:20:39 +00:00
Katherine Parry
09564f1c77
fixed various bugs
2021-03-04 22:20:28 +00:00
Katherine Parry
a6bc39b5ad
fixed various bugs
2021-03-04 22:20:23 +00:00
Katherine Parry
526e3f5996
fixed various bugs
2021-03-04 22:20:02 +00:00
Katherine Parry
1e906b36a0
fixed various bugs
2021-03-04 22:19:21 +00:00
Katherine Parry
3fb0f323b8
fixed various bugs
2021-03-04 22:18:47 +00:00
Katherine Parry
fdfc0dbf46
fixed various bugs
2021-03-04 22:18:19 +00:00
Thomas Fleming
3303a013ef
Merge branch 'walker' into main
2021-03-04 15:27:03 -05:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7
Fixed forwarding around the 2 bit predictor.
2021-03-04 13:01:41 -06:00
Ross Thompson
52d95d415f
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Thomas Fleming
de3f2547f4
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6
Install tlb into ifu
2021-03-04 03:11:34 -05:00
Thomas Fleming
2e409f2299
Merge branch 'tlb_toy' into main
2021-03-04 02:41:11 -05:00
Thomas Fleming
5f98c932bf
Move tlb into mmu directory
2021-03-04 02:39:08 -05:00
Teo Ene
f060f6cb9d
Fix to 32-bit option of commit babe6ce9db
2021-03-04 01:33:34 -06:00
Thomas Fleming
d9f396ee0e
Merge branch 'main' into tlb_toy
2021-03-04 01:18:04 -05:00
Thomas Fleming
347275e7ee
Generalize tlb module
...
- number of tlb entries is now parameterized
- tlb now supports rv64i
2021-03-04 01:13:31 -05:00
Thomas Fleming
394051c02f
Begin hardware page table walker
2021-03-03 17:13:45 -05:00
David Harris
9bcddfa5dd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-01 00:09:55 -05:00
David Harris
2543c29839
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Teo Ene
babe6ce9db
Properly implemented the fix from commit 31c07b2adc
2021-02-28 22:22:04 -06:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
David Harris
cf03afa880
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
015b632eb1
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
b16846bddb
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
24f767a404
Retimed peripherals for AHB interface
2021-02-26 00:55:41 -05:00
David Harris
c060e427f0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-25 15:49:38 -05:00
David Harris
a16fd95eed
Restored to working multiplier after Lab 2
2021-02-25 15:32:43 -05:00
Brett Mathis
ec82453ba1
FPU Assembly tests
2021-02-25 14:32:36 -06:00
Teo Ene
6be5bb1f84
Fixed previous commit
2021-02-25 11:24:44 -06:00
Teo Ene
31c07b2adc
Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.
2021-02-25 11:23:01 -06:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Katherine Parry
8f5cc19143
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-23 20:21:53 +00:00
Katherine Parry
7b103423e1
inital FMA push
2021-02-23 20:19:12 +00:00
David Harris
c52a99ce2d
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
817f81c356
Debugging Bus interface
2021-02-22 13:48:30 -05:00
Ross Thompson
9b3637bd87
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87
Added FlushF to hazard unit.
...
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
c6ebe7733b
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
...
About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Thomas Fleming
21552eaf9d
Create simple TLB
...
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
2021-02-18 18:06:09 -05:00
David Harris
acd7ba8b60
Updated creation date of mul
2021-02-18 08:13:08 -05:00
Ross Thompson
5df7e959f3
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
David Harris
2f5b4c3a25
Resotred part of multiplier for lab 2
2021-02-17 16:14:04 -05:00
David Harris
64536dbc34
Removed multiplier for lab 2
2021-02-17 16:06:16 -05:00
