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Author SHA1 Message Date
Thomas Fleming
2e2eb5839f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
8c97143be6 Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
7e11317a2d Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Ross Thompson
a662aa487c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Ross Thompson
264480f258 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Katherine Parry
cfac6bf0c7 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
09564f1c77 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
a6bc39b5ad fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
526e3f5996 fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
1e906b36a0 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
3fb0f323b8 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
fdfc0dbf46 fixed various bugs 2021-03-04 22:18:19 +00:00
Ross Thompson
fafecb5f01 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 16:06:22 -06:00
Brett Mathis
57e484cd55 Pipelined functional units for FPU 2021-03-04 14:30:11 -06:00
Thomas Fleming
3303a013ef Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Thomas Fleming
1fb50aff6b Add reference output for mmu test 2021-03-04 15:17:49 -05:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7 Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Thomas Fleming
7347b3e1b7 Fix some constants in virtual memory test 2021-03-04 13:19:55 -05:00
bbracker
448cba2a5b JALR testing 2021-03-04 10:37:30 -05:00
bbracker
d98c69c4c6 changed test maker to output trace files for debug 2021-03-04 10:36:04 -05:00
Ross Thompson
52d95d415f Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
de3f2547f4 Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
2e409f2299 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
5f98c932bf Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
f060f6cb9d Fix to 32-bit option of commit babe6ce9db 2021-03-04 01:33:34 -06:00
Thomas Fleming
d9f396ee0e Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
347275e7ee Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Thomas Fleming
394051c02f Begin hardware page table walker 2021-03-03 17:13:45 -05:00
Thomas Fleming
d8ac9034b7 Create virtual memory ad-hoc test 
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
 2021-03-03 17:06:37 -05:00
Teo Ene
4562c61af3 Fix to last push 2021-03-03 15:20:38 -06:00
Teo Ene
37bf3d836f Updated coremark .do file for easier debugging 2021-03-03 15:10:39 -06:00
Teo Ene
e6044b9867 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-02 17:23:44 -06:00
Teo Ene
e7f7f980b3 Updated coremark .do file for easier debugging 2021-03-02 17:23:39 -06:00
David Harris
9bcddfa5dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-01 00:09:55 -05:00
David Harris
2543c29839 Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Teo Ene
babe6ce9db Properly implemented the fix from commit 31c07b2adc 2021-02-28 22:22:04 -06:00
Noah Boorstin
1858c32e9d add .nfs* files to gitignore 2021-02-28 20:48:01 +00:00
Ross Thompson
7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
cf03afa880 Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
015b632eb1 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
David Harris
b16846bddb Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
24f767a404 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
Brett Mathis
4e6caf64d9 Fcmp/Fsgn pipeline modules 2021-02-25 18:22:30 -06:00
David Harris
c060e427f0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
a16fd95eed Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
ec82453ba1 FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
6be5bb1f84 Fixed previous commit 2021-02-25 11:24:44 -06:00