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https://github.com/openhwgroup/cvw
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Create simple TLB
This TLB is just a demonstration and is not currently instantiated by the IFU or DFU.
This commit is contained in:
Thomas Fleming
parent
2f5b4c3a25
commit
21552eaf9d
53
wally-pipelined/src/tlb_toy/tlb_testbench.sv
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53
wally-pipelined/src/tlb_toy/tlb_testbench.sv
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module testbench();
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logic clk, reset;
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// DUT inputs
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logic [31:0] PCF;
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logic [31:0] PageTableEntryF;
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logic ITLBWriteF, ITLBFlushF;
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// DUT outputs
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logic [31:0] PCPF;
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logic ITLBMissF, ITLBHitF;
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// Testbench signals
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logic [33:0] expected;
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logic [31:0] vectornum, errors;
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logic [99:0] testvectors[10000:0];
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// instantiate device under test
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tlb_toy dut(.*);
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// generate clock
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always begin
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clk=1; #5; clk=0; #5;
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end
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// at start of test, load vectors and pulse reset
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initial begin
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$readmemb("tlb_toy.tv", testvectors);
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vectornum = 0; errors = 0; reset = 1; #22; reset = 0;
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end
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// apply test vectors on rising edge of clk
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always @(posedge clk) begin
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#1; {PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF, expected} = testvectors[vectornum];
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end
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// check results on falling edge of clk
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always @(negedge clk)
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if (~reset) begin // skip during reset
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if ({PCPF, ITLBMissF, ITLBHitF} !== expected) begin // check result
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$display("Error: PCF = %b, write = %b, data = %b, flush = %b", PCF,
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ITLBWriteF, PageTableEntryF, ITLBFlushF);
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$display(" outputs = %b %b %b (%b expected)",
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PCPF, ITLBMissF, ITLBHitF, expected);
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errors = errors + 1;
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end
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vectornum = vectornum + 1;
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if (testvectors[vectornum] === 100'bx) begin
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$display("%d tests completed with %d errors", vectornum, errors);
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$stop;
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end
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end
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endmodule
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208
wally-pipelined/src/tlb_toy/tlb_toy.sv
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208
wally-pipelined/src/tlb_toy/tlb_toy.sv
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///////////////////////////////////////////
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// tlb_toy.sv
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//
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// Written: jtorrey@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Example translation lookaside buffer
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// Cache of virtural-to-physical address translations
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// `include "wally-config.vh"
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/**
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* sv32 specs
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* ----------
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* Virtual address [31:0] (32 bits)
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* [________________________________]
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* |--VPN1--||--VPN0--||----OFF---|
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* 10 10 12
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*
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* Physical address [33:0] (34 bits)
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* [__________________________________]
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* |---PPN1---||--PPN0--||----OFF---|
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* 12 10 12
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*
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* Page Table Entry [31:0] (32 bits)
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* [________________________________]
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* |---PPN1---||--PPN0--|||DAGUXWRV
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* 12 10 ^^
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* RSW(2) -- for OS
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*/
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/* *** TODO:
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* - add LRU algorithm (select the write index based on which entry was used
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* least recently)
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* - rename signals to use .* notation in CAM and RAM
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*/
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module tlb_toy (
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input clk, reset,
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// Virtual address input
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input [31:0] PCF,
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// Controls for writing a new entry to the TLB
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input [31:0] PageTableEntryF,
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input ITLBWriteF,
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// Invalidate all TLB entries
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input ITLBFlushF,
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// Physical address outputs
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output [31:0] PCPF,
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output ITLBMissF,
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output ITLBHitF
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);
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// Index (currently random) to write the next TLB entry
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logic [2:0] WriteIndexF;
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// Sections of the virtual and physical addresses
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logic [19:0] VirtualPageNumberF;
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logic [21:0] PhysicalPageNumberF;
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logic [11:0] PageOffsetF;
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logic [33:0] PhysicalAddressF;
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// Pattern and pattern location in the CAM
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logic [2:0] VPNIndexF;
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// RAM access location
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logic [2:0] ITLBEntryIndex;
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// Page table entry matching the virtual address
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logic [31:0] PTEMatchF;
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assign VirtualPageNumberF = PCF[31:12];
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assign PageOffsetF = PCF[11:0];
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// Choose a read or write location to the entry list
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mux2 #(3) indexmux(VPNIndexF, WriteIndexF, ITLBWriteF, ITLBEntryIndex);
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// Currently use random replacement algorithm
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rand3 rdm(clk, reset, WriteIndexF);
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ram8x32 ram(clk, reset, ITLBEntryIndex, PageTableEntryF, ITLBWriteF, PTEMatchF);
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cam8x21 cam(clk, reset, ITLBWriteF, VirtualPageNumberF, WriteIndexF,
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ITLBFlushF, VPNIndexF, ITLBHitF);
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always_comb begin
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assign PhysicalPageNumberF = PTEMatchF[31:10];
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if (ITLBHitF) begin
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assign PhysicalAddressF = {PhysicalPageNumberF, PageOffsetF};
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end else begin
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assign PhysicalAddressF = 34'b0;
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end
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end
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assign PCPF = PhysicalAddressF[31:0];
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assign ITLBMissF = ~ITLBHitF & ~(ITLBWriteF | ITLBFlushF);
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endmodule
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// *** Add parameter for number of tlb lines (currently 8)
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module ram8x32 (
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input clk, reset,
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input [2:0] address,
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input [31:0] data,
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input we,
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output [31:0] out_data
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);
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logic [31:0] ram [0:7];
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always @(posedge clk) begin
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if (we) ram[address] <= data;
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end
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assign out_data = ram[address];
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initial begin
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for (int i = 0; i < 8; i++)
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ram[i] = 32'h0;
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end
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endmodule
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module cam8x21 (
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input clk, reset, we,
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input [19:0] pattern,
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input [2:0] write_address,
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input ITLBFlushF,
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output [2:0] matched_address,
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output match_found
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);
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logic [20:0] ram [0:7];
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logic [7:0] match_line;
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logic [2:0] matched_address_comb;
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logic match_found_comb;
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always @(posedge clk) begin
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if (we) ram[write_address] <= {1'b1,pattern};
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if (ITLBFlushF) begin
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for (int i = 0; i < 8; i++)
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ram[i][20] = 1'b0;
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end
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end
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// *** Check whether this for loop synthesizes correctly
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always_comb begin
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match_found_comb = 1'b0;
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matched_address_comb = 3'b0;
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for (int i = 0; i < 8; i++) begin
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if (ram[i] == {1'b1,pattern} && !match_found_comb) begin
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matched_address_comb = i;
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match_found_comb = 1;
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end else begin
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matched_address_comb = matched_address_comb;
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match_found_comb = match_found_comb;
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end
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end
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end
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assign matched_address = matched_address_comb;
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assign match_found = match_found_comb & ~(we | ITLBFlushF);
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initial begin
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for (int i = 0; i < 8; i++)
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ram[i] <= 0;
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end
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endmodule
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module mux2 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule
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module rand3 (
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input clk, reset,
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output [2:0] WriteIndexF
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);
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logic [31:0] data;
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assign data = $urandom;
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assign WriteIndexF = data[2:0];
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endmodule
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11
wally-pipelined/src/tlb_toy/tlb_toy.tv
Normal file
11
wally-pipelined/src/tlb_toy/tlb_toy.tv
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@ -0,0 +1,11 @@
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// tlb_toy.tv
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// PCF _ PageTableEntryF _ ITLBWriteF _ ITLBFlushF ___ PCPF _ ITLBMissF _ ITLBHitF
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10101010101010101010101010101010_00000000000000000000000000000000_0_0___00000000000000000000000000000000_1_0
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// Write test: Add translation aaaaa -> 044444 to TLB
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10101010101010101010101010101010_00010001000100010001001100110010_1_0___00000000000000000000000000000000_0_0
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10101010101010101010101010101010_00000000000000000000000000000000_0_0___01000100010001000100101010101010_0_1
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10101010101010101010101010101010_00000000000000000000000000000000_0_0___01000100010001000100101010101010_0_1
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10101010100010101010101010101010_00000000000000000000000000000000_0_0___00000000000000000000000000000000_1_0
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// Flush test: should invalidate all entries
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00000000000000000000000000000000_00000000000000000000000000000000_0_1___00000000000000000000000000000000_0_0
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10101010101010101010101010101010_00000000000000000000000000000000_0_0___00000000000000000000000000000000_1_0
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