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Author	SHA1	Message	Date
David Harris	2d7f4b133c	More work toward riscof tests	2022-07-26 06:19:13 -07:00
David Harris	c6a58eb5b6	Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd	2022-07-25 16:23:10 -07:00
David Harris	416f5edfe0	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
David Harris	7f7b3359b0	Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings	2022-07-25 20:50:38 +00:00
David Harris	62be9963d8	Fixed synthesis by removing wally-config.vh at level above hdl directory	2022-07-25 01:50:38 +00:00
Ross Thompson	8193946996	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-23 08:41:59 -05:00
Ross Thompson	05484c4c05	signal name cleanup.	2022-07-22 23:36:27 -05:00
Ross Thompson	27e32980ad	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	17ae1a1b1b	cache fsm cleanup after removal of replay.	2022-07-22 23:25:09 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Katherine Parry	655e2d3810	merged radix-2 sqrt into divider - doesnt work yet	2022-07-23 00:41:18 +00:00
slmnemo	bfced6bfe8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-22 17:13:38 -07:00
slmnemo	ca4511b6dc	Fixed UART FIFO bugs and added FIFO tests	2022-07-22 17:13:19 -07:00
Daniel Torres	d0aaae26fe	fixed wally rv32e tests, updated regression makefile to new testflow	2022-07-22 17:09:46 -07:00
Daniel Torres	35878755f5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 15:35:25 -07:00
Daniel Torres	4da96c5791	fixed 32priv tests, now passing	2022-07-22 15:35:20 -07:00
Katherine Parry	b3d932cd61	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
Daniel Torres	24828db612	changes to test.vh for compatability	2022-07-22 15:00:48 -07:00
Daniel Torres	4198145ce2	added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail	2022-07-22 14:58:55 -07:00
slmnemo	ba2dcf6da4	fixed error in tests.vh	2022-07-22 14:55:55 -07:00
slmnemo	ec1ed5bd94	Added UART test to peripheral test	2022-07-22 14:55:34 -07:00
slmnemo	141f2a40e4	UART updates and PMA fix	2022-07-22 14:49:03 -07:00
Daniel Torres	574e603d69	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 13:52:19 -07:00
Daniel Torres	139e657fcc	commented out embench test that should be commented out	2022-07-22 13:52:13 -07:00
slmnemo	df411497e0	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-22 12:36:06 -07:00
slmnemo	9cca567136	Added test comments to reference output	2022-07-22 12:35:59 -07:00
slmnemo	cb16a75119	Added PLIC test to regression	2022-07-22 12:35:37 -07:00
Daniel Torres	0e75142ef4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 11:16:09 -07:00
Daniel Torres	95fdd408ee	commiting current changes to riscof wally tests	2022-07-22 11:14:04 -07:00
cturek	e2691c02b7	Square root negative exponent handling	2022-07-22 16:45:19 +00:00
slmnemo	d38369e8bf	Added new PLIC and UART tests	2022-07-22 07:12:55 -07:00
slmnemo	df568fd202	Added PLIC and UART tests and new functions to the test library	2022-07-22 07:10:39 -07:00
David Harris	d22587090b	Reset MSR on read	2022-07-22 04:29:27 +00:00
Daniel Torres	c29a60c198	changed gitignore, updated version of arch tests on main build	2022-07-21 21:10:15 -07:00
Daniel Torres	ae0f8de2b5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 20:59:01 -07:00
Daniel Torres	8dcb794bbb	added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64	2022-07-21 20:58:58 -07:00
slmnemo	95822b77f0	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-21 20:35:52 -07:00
slmnemo	3d2c6683d8	Fixed UART bug related to parity and MSR/LSR	2022-07-21 20:35:46 -07:00
cturek	8bfb233204	Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder	2022-07-22 01:27:08 +00:00
cturek	c7e84f8e40	Renamed variables, moved output handling to postprocessor, added remainder handling	2022-07-21 20:45:08 +00:00
Daniel Torres	9421b77613	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 12:50:04 -07:00
Daniel Torres	635a02cf6a	made makefile more specific, just incase future additions	2022-07-21 12:50:02 -07:00
Daniel Torres	a8faddf81f	removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes	2022-07-21 12:47:51 -07:00
Katherine Parry	0630e2a9a2	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-21 19:38:15 +00:00
Katherine Parry	fbe8bb2298	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
cturek	86ebdd05f0	Division working too	2022-07-21 17:59:10 +00:00
cturek	4793267bd7	Updated Radix2 Sqrt to follow new algorithm	2022-07-21 17:36:21 +00:00
Daniel Torres	16e4260dda	fixed gitmodules	2022-07-21 10:15:13 -07:00
Daniel Torres	7f447853c3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 10:14:20 -07:00
Daniel Torres	e46e96e080	changed the default branch of embench	2022-07-21 10:14:05 -07:00