Github_Repos/cvw
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8,256 Commits 4 Branches 2 Tags 52 MiB
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88 Commits

Author SHA1 Message Date
Rose Thompson
6110799a1e Updated the wally rv32 priv tests to not use sail. 2024-02-16 11:39:06 -06:00
David Harris
430d495ce5 Updated to latest riscv-arch-test 2023-12-31 10:04:20 -08:00
Rose Thompson
e38b43ae73 Replaced the git@github with hptts:github submodule for ahbsdc which I hope will fix Lee's clone issue 2023-12-11 14:12:38 -06:00
David Harris
d8186b9f58 Swap in branch predictor simulator handling compressed instruction offsets 2023-11-21 16:42:41 -08:00
David Harris
93a0db1fca swapped branch predictor simulator 2023-11-21 15:02:09 -08:00
David Harris
2b2016271a repo cleanup and start to add CMO tests 2023-11-20 23:41:36 -08:00
David Harris
8cb433cb66 Commented IROM preloading 2023-11-19 19:33:57 -08:00
Jacob Pease
a1e7158bd9 Merge branch 'main' of github.com:openhwgroup/cvw 2023-11-18 19:20:48 -06:00
Jacob Pease
38cf7f0fb7 ahbsdc submodule actually added this time. 2023-11-16 17:46:48 -06:00
Jacob Pease
9df87872ef Deleted vivado-risc-v directory and added ahbsdc. 2023-11-16 15:13:12 -06:00
David Harris
7b2bb86ced changed to head of riscv-arch-test 2023-11-15 09:48:13 -08:00
David Harris
90cf128349 Added back riscv-arch-test fresh 2023-11-15 05:48:33 -08:00
David Harris
18c29dd7d0 Removed riscv-arch-test submodule that appears corrupted 2023-11-15 05:46:38 -08:00
David Harris
8ba0336c6f Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e 2023-11-14 11:01:58 -08:00
naichewa
75f1c07022 merge main, pull /A/ tests 2023-11-03 13:16:19 -07:00
Ross Thompson
b1f7a5768f Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
026570d3da Added new submodule for digilent fpga boards. 2023-07-17 16:25:37 -05:00
Victor Clements
9461b9db7e pulling in FreeRTOS/kernel Submodule 2023-06-13 10:41:18 -07:00
David Harris
98a44fd3bd wally installation improvements: latest main branch of riscv-arch-test, updated install script 2023-05-10 08:23:55 -07:00
Ross Thompson
f067935eed Added Yujun Lin's branch predictor simulator. This is a C baseline module for common branch predictor algorithms. 2023-03-07 10:49:59 -06:00
David Harris
906e74dac2 Pulled to latest commit of riscv-arch-test 2023-02-28 15:03:59 -08:00
James Stine
8b4c3920db Update Appendix D + wrapped memories 2023-01-28 19:46:43 -06:00
David Harris
5df4679bcb Removed old link to imperas-riscv-tests 2023-01-26 14:53:25 -08:00
James Stine
a5d402c6ce This adds the Dockerfile for those who might be interested in building a docker container for Wally 2023-01-23 17:29:58 -06:00
David Harris
1ec62606f9 sram1p1rw cleanup 2022-12-20 02:57:51 -08:00
Ross Thompson
fc05e27416 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
David Harris
f326b18af6 embench cleaned up 2022-09-08 11:38:01 -07:00
Katherine Parry
655e2d3810 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
c29a60c198 changed gitignore, updated version of arch tests on main build 2022-07-21 21:10:15 -07:00
Katherine Parry
fbe8bb2298 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Daniel Torres
e46e96e080 changed the default branch of embench 2022-07-21 10:14:05 -07:00
David Harris
e22d6a2f9a Removed Sky130 libraries 2022-07-06 13:50:11 +00:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Madeleine Masser-Frye
59a514ae81 remove run deletion with wally synthesis 2022-06-17 19:45:38 +00:00
DTowersM
7c0f4dd954 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 23:34:35 +00:00
DTowersM
39ed36d0ba added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
Katherine Parry
5f7072bd96 postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
Madeleine Masser-Frye
5a9f1a3970 update 2022-06-03 21:17:50 +00:00
Katherine Parry
559c0c278e added unpackinput.sv 2022-05-31 16:18:50 +00:00
Madeleine Masser-Frye
d5e0eb9eb4 added optimized area plotting 2022-05-30 18:54:02 +00:00
Katherine Parry
835a4e4606 fixed lint error 2022-05-28 10:20:13 -07:00
Madeleine Masser-Frye
4ed7283ad1 fixed normalization vertical axes, added TechSpecs type 2022-05-28 04:57:18 +00:00
Katherine Parry
d5c249bf71 unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
3c63db9554 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
cturek
0f1da722bf Set up the divider for on-the-fly conversion 2022-05-26 16:45:28 +00:00
Katherine Parry
f4b9ade942 added fcvt.sv 2022-05-26 00:10:51 +00:00
cturek
650779318d Fixed exponent verification, added sign module and added sign tests 2022-05-25 23:36:21 +00:00
Katherine Parry
c264585fe8 single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
378523087f added widths for csa in ppa 2022-05-22 23:23:02 +00:00