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1,746 Commits 4 Branches 2 Tags 53 MiB
2d09994a91
Commit Graph

956 Commits

Author SHA1 Message Date
David Harris
2d09994a91 Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
644af40855 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
e93014d6d8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
e8d013b106 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
David Harris
99fd79c20b Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
5cb30164d4 renamed DivSigned 2021-10-10 08:30:19 -07:00
bbracker
25e0745a6a fix div restarting bug 2021-10-07 18:55:00 -04:00
James E. Stine
b90d7b8083 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
David Harris
cc41d40d61 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
3398328bf1 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
5022647041 Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit f6ef8e5656.
 2021-09-30 20:45:26 -04:00
David Harris
a39e14663d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
Ross Thompson
d09b381183 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872 Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Ross Thompson
8fa287a449 The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
b92070a67a Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
55cbd957f0 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
4ca0c0ea7d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
eb7b5f1d63 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
David Harris
72c1cc33f5 Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
David Harris
654f3d1940 Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00