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540 Commits

Author SHA1 Message Date
David Harris
36a825c43b Improved CSRU coverage with priv.S 2023-08-20 12:49:31 -07:00
harshinisrinath
2c2c117201 wrote testcase to write into FSCR 2023-08-20 12:10:08 -07:00
Ross Thompson
6337aab757 Fixed issue when with flush miss. 2023-08-18 16:36:13 -05:00
Ross Thompson
e3bb0d2820 Now we have invalidate, clean, and flush working. 2023-08-18 16:32:22 -05:00
Ross Thompson
b9af790b81 Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. 2023-08-18 15:59:39 -05:00
harshinisrinath
15dbbef9ad Fixed bug and tried to reset menvcfg to improve testing of csri in priv. 2023-07-30 16:40:06 -07:00
harshinisrinath
24792d82e9 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-07-23 11:59:43 -07:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Jacob Pease
142ec857ed Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
harshinisrinath
cba045b53c Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-07-13 13:00:58 -07:00
Kevin Kim
7e185a2f0d fixed bug in testvector extract script 
-old script skips first 2 lines in rv32m case, new script only skips first line
- prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer
- prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
 2023-06-22 09:13:22 -07:00
harshinisrinath
dc6633c796 Improved testing of pmd in priv. 2023-06-16 17:13:54 -07:00
harshinisrinath
c9695e6813 Improve test coverage on ieu fw. 2023-06-16 16:09:48 -07:00
David Harris
b20363f9c2 Fixed timer interrupt testing 2023-06-09 17:20:41 -07:00
David Harris
9373ad3811 Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
David Harris
b15c5e2a51 Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare 2023-06-09 14:40:01 -07:00
Ross Thompson
f4883e31df
Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
James Stine
736ae7d749 Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing 2023-06-05 11:03:59 -05:00
David Harris
c1e7332abf Fixed paths in creating division test vectors 2023-05-31 06:30:41 -07:00
David Harris
8c1bd8523a Clean up combined int/fp vector creation 2023-05-30 14:01:12 -07:00
Jacob Pease
2ad9c72acc The Vivado-RISC-V SDC works. Wally is now booting through it. 2023-05-26 15:42:33 -05:00
David Harris
e2c990f47d Increased timeout for riscof because it is so slow 2023-05-23 15:37:09 -07:00
David Harris
bdd0ab5a55 Added Zifencei ISA to tests where necessary to support new compiler 2023-05-16 11:18:27 -07:00
David Harris
f5db0a714d Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile 2023-05-14 06:58:29 -07:00
David Harris
402395b126 Fixed riscof scripts that were removing zicsr from compiler misa 2023-05-14 04:19:08 -07:00
David Harris
c6a6269404 Defined empty RVMODEL interrupt macros to make riscof warnings go away 2023-05-14 03:36:28 -07:00
Kevin Thomas
968c228fcc Comment tlbGBL more discriptively 
Reduce redundant instructions
 2023-05-04 19:13:47 -05:00
David Harris
2b9b2f21df
Merge branch 'main' into main 2023-04-28 07:51:32 -07:00
Liam Chalk
8ef9e77e00
Merge branch 'main' into main 2023-04-27 21:49:01 -07:00
Kevin Wan
c0cbd0fd2a added tests for pmppriority module 2023-04-27 16:12:43 -07:00
David Harris
c04f636952
Update tlbASID.S 
fixed comment about restoring ASID to 0
 2023-04-27 14:32:57 -07:00
Noah Limpert
26cb639f89 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Liam
6803347a49 Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
Alexa Wright
667c54c129
Merge branch 'openhwgroup:main' into main 2023-04-26 16:26:30 -07:00
Alexa Wright
55a74fd315 Excluded and added coverage for WFI test case. 2023-04-25 17:06:57 -07:00
Liam
309a56b8f8 pmpaddr0 and pmpaddr2 test cases 
Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
 2023-04-25 15:37:04 -07:00
David Harris
8be5ed9b67 Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
Liam
2ed9384238 pmpcfg test cases 
Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
 2023-04-21 20:43:37 -07:00
Noah Limpert
cf150a2ea9 Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
73cca666bf Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
Liam
2684a81754 Add pmpcfg test cases increasing IFU coverage 2023-04-19 11:58:22 -07:00
David Harris
79dbfae4af
Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
59d153ace0
Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
Alec Vercruysse
3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
777028e43b Add test cases for pmpcfg.S 2023-04-18 23:06:52 -07:00
Kevin Wan
fe51108740 a 2023-04-18 22:09:50 -07:00
Kevin Wan
fed7681695 Merge branch 'main' of https://github.com/koooo142857/cvw into main 2023-04-18 21:55:06 -07:00
koooo142857
ea39b53c97
Merge branch 'openhwgroup:main' into main 2023-04-18 21:53:46 -07:00
Kevin Wan
20a0803f46 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
3ef81f4e6a PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Miles Cook
5cfd0577d1 Increase of TLB coverage in IFU 2023-04-17 18:35:03 -07:00
Diego Herrera Vicioso
34dd481f93 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00
Dygore
92a0827d80 Added multiple tests to increase FPU coverage 2023-04-14 14:41:05 -05:00
Dylan
4c91bb3b76
Merge branch 'openhwgroup:main' into main 2023-04-14 00:36:57 -05:00
Dygore
23dbca3991 Added tests for full coverage of the FPU result sign module 2023-04-14 00:36:12 -05:00
Noah Limpert
30ed9c2b69 add back K. Box and M. Cook Lsu test 2023-04-13 17:50:18 -07:00
Noah Limpert
187c5b07c7 make pull request more clean 2023-04-13 17:44:09 -07:00
Noah Limpert
c76de00d60 Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways" 
This reverts commit 0fea40282a.
 2023-04-13 17:40:39 -07:00
Noah Limpert
4ab27b4f12 Revert "Test File for Pull Request, Attempt to fill all four ways" 
This reverts commit f770243689.
 2023-04-13 17:28:37 -07:00
Noah Limpert
bcbbcd5a30 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-13 17:00:48 -07:00
Noah Limpert
98420e45ac update tests.vh, add tlbKP to load all lines of tlb 2023-04-13 15:13:55 -07:00
Dygore
3d5c128470 Added a test for denormalized FP numbers 2023-04-13 16:39:27 -05:00
Noah Limpert
3a06ec7094 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 
pull in changes to trap handler so that permissions should change correctly
 2023-04-13 12:34:27 -07:00
Alexa Wright
f8a8c43307 Fixed exception handling to handle ecalls properly 2023-04-13 09:23:32 -07:00
Kip Macsai-Goren
9f30414e97 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
7d9ebf56ed renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
cf50d04a21 removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
b839de4451 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
c179d76542 Removed Trap outputs from writes covered by SVADU 2023-04-11 17:41:57 -07:00
Kip Macsai-Goren
41ef59ddfe Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
4bf2a7e15b Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
Noah Limpert
a7ec77239f Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-10 19:01:32 -07:00
David Harris
a819a24b83
Merge pull request #226 from SydRiley/main 
Increased coverage for the fpu by adding directed tests to toggle signals
 2023-04-09 21:52:11 -07:00
Kevin Box
f74bb8b38e Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
Noah Limpert
06a138e6d9 3rd attempt to resolve conflict in lsu.S file 2023-04-09 15:52:18 -07:00
Sydeny
ff405a49a5 Increasing coverage for the fpu by adding directed tests to toggle signals 2023-04-09 13:33:12 -07:00
Diego Herrera Vicioso
76d5c3e500 Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs. 2023-04-08 16:40:36 -07:00
David Harris
a9b7bd101e Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
David Harris
25f394ce97 Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf 2023-04-07 21:11:01 -07:00
David Harris
5c6d9f87a0 Fixed priv.S to initialize stimecmp and agree with ImperasDV 2023-04-07 20:44:01 -07:00
David Harris
8b4016582b Fixed WALLY-init-lib to return correctly even from traps from compressed instructions 2023-04-07 20:24:33 -07:00
David Harris
982ade31c5 Fixed enabling machine timer interrupt 2023-04-06 22:18:33 -07:00
David Harris
c9887cb182 vm64 tests 2023-04-06 21:42:47 -07:00
Jacob Pease
2b9e5608a4 Build doesn't work. AXI Crossbar has problems. 2023-04-06 16:01:58 -05:00
David Harris
b3cf1b45fa
Merge pull request #210 from SydRiley/main 
Starting to extend fpu conditional coverage, reformatting ifu test cases.
 2023-04-05 14:56:16 -07:00
Sydeny
d264d3274c Starting to extend fpu conditional coverage, reformating ifu test cases 2023-04-05 14:10:15 -07:00
David Harris
7963bfdbe5
Merge pull request #205 from kbox13/my-single-change 
Increase LSU Coverage
 2023-04-05 13:16:04 -07:00
Limnanthes Serafini
5bae4801bb
*.out removal 2023-04-05 12:50:26 -07:00
Limnanthes Serafini
69eecac989
*.out removal 2023-04-05 12:50:10 -07:00
Limnanthes Serafini
6f53531e26
*.out removal 2023-04-05 12:49:57 -07:00
Kevin Box
c43ee180d3 Add sfence.vma 2023-04-05 10:34:30 -07:00
Kevin Box
490cebe36b Revert "Add sfence.vma and arch64d/f tests to increase coverage in the LSU" 
This reverts commit 90b5d279fd.
 2023-04-05 10:32:25 -07:00
Kevin Box
90b5d279fd Add sfence.vma and arch64d/f tests to increase coverage in the LSU 2023-04-05 10:18:41 -07:00
Limnanthes Serafini
98a56dcd66 Further comments and attribution. 2023-04-05 02:46:31 -07:00
Limnanthes Serafini
47a8cf3993 Outfiles for the failing tests. 2023-04-05 02:42:09 -07:00
Limnanthes Serafini
8f3413f0d5 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00
Noah Limpert
77bd9824c5 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-04 20:22:00 -07:00
Noah Limpert
f770243689 Test File for Pull Request, Attempt to fill all four ways 2023-04-03 21:54:27 -07:00